Computer-Aided Design of Sequential Logic Circuits (Case of Asynchronous Sequential Logic Circuits)

컴퓨터를 이용한 순차 논리 회로의 설계(비동기 순차논리 회로의 경우

This paper is concerned with a computer-aided state assignment, that is, coding race-free internal states of asynchronous sequential circuits, and a method for minimizing the combinational network of asynchronous sequential circuits. The FORTRAN version of the peoposed algorithm results in race-free state assignments and reduction of the number of connections and gates with near minimal hardware cost. Some examples are designed by the proposed computer program to illustrate the algorithm in this paper. Finally, results are compared with those of the other methods.