• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.7
• /
• pp.30-36
• /
• 2010

Due to the scaling of process parameters, the density on chips has been increasing. This trend increases not only the temperature on chips but also the gradient of the temperature depending on distances. In this paper, we propose the balanced skew tree generation technique for minimizing the clock skew that is affected by the temperature gradients on chips. We calculate the interconnect delay using Elmore delay equation, and find out the optimal balanced clock tree by modifying the clock trees that are generated through the DME(Deferred Merge Embedding) algorithm. We have implemented the proposed technique using C language for the performance evaluation. The experimental results show that the clock insertion point generated by the temperature gradient can be lowered below 54% and we confirm that the skew is remarkably decreased after applying the proposed technique.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.10
• /
• pp.63-68
• /
• 2004

A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the infernal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the SMD. Fine locking is achieved by the successive approximation register-controlled DLL. The total locking time is 10 clock cycles. Simulation results show that the proposed SMD operates with 50psec clock skew at 182MHz and consumes 17.5mW at 3.3V supply voltage in a 0.35 um 1-poly 4-metal CMOS technology.

• Journal of Information Processing Systems
• /
• v.16 no.3
• /
• pp.541-556
• /
• 2020

Wireless networks have become integral to society as they provide mobility and scalability advantages. However, their disadvantage is that they cannot control the media, which makes them vulnerable to various types of attacks. One example of such attacks is the evil twin access point (AP) attack, in which an authorized AP is impersonated by mimicking its service set identifier (SSID) and media access control (MAC) address. Evil twin APs are a major source of deception in wireless networks, facilitating message forgery and eavesdropping. Hence, it is necessary to detect them rapidly. To this end, numerous methods using clock skew have been proposed for evil twin AP detection. However, clock skew is difficult to calculate precisely because wireless networks are vulnerable to noise. This paper proposes an evil twin AP detection method that uses a multiple-feature-based machine learning classification algorithm. The features used in the proposed method are clock skew, channel, received signal strength, and duration. The results of experiments conducted indicate that the proposed method has an evil twin AP detection accuracy of 100% using the random forest algorithm.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.9 no.1
• /
• pp.29-36
• /
• 2009

Power supply noise is fundamentally caused by large current peaks. Since large current peaks are induced by simultaneous switching of many circuit elements, power supply noise can be minimized by deliberate clock scheduling which utilizes nonzero clock skew. In this paper, nonzero skew clock scheduling is used to avoid the large peak current and consequently reduce power supply noise. While previous approaches require extra characterization efforts to acquire current waveform of a circuit, we approximate it only with existing cell library information to be easily adapted to conventional design flow. A simulated annealing based algorithm is performed, and the peak current values are estimated for feasible clock schedules found by the algorithm. The clock schedule with the minimum peak current is selected for a solution. Experimental results on ISCAS89 benchmark circuits show that the proposed method can effectively reduce the peak current.

• Journal of KIISE:Information Networking
• /
• v.34 no.5
• /
• pp.370-378
• /
• 2007

In wireless sensor networks (WSNs), thousands of sensors are often deployed in a hostile environment. In such an environment, WSNs can be applied to various applications by using the absolute or relative location information of the sensors. Until now, the time-of-arrival (TOA) based localization method has been considered most accurate. In the TOA method, however, inaccuracy in distance estimation is caused by clock drift and clock skew between sensor nodes. To solve this problem, several numbers of periodic time synchronization methods were suggested while these methods introduced overheads to the packet traffic. In this paper, we propose a new localization method based on multiple round-trip times (RTOA) of a signal which gives more accurate distance and location estimation even in the presence of clock skew between sensor nodes. Our experimental results show that the Proposed RTOA method gives up to 93% more accurate location estimation.

• Journal of Korea Multimedia Society
• /
• v.15 no.11
• /
• pp.1391-1398
• /
• 2012

Time synchronization is crucial in wireless sensor networks such as Wireless USB and WBAN for diverse purposes from the MAC to the application layer. This paper proposes online clock skew estimators to achieve energy-efficient time synchronization for wireless sensor networks. By using recursive least squares estimators, we not only reduce the amount of data which should be stored locally in a table at each sensor node, but also allow offset and skew compensations to be processed simultaneously. Our skew estimators can be easily integrated with traditional offset compensation schemes. The results of simulation and experiment show that the accuracy of time synchronization can be greatly improved through our skew compensation algorithm.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.56 no.6
• /
• pp.1133-1138
• /
• 2007

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.7
• /
• pp.74-80
• /
• 2002

VLSI intergrated circuits like SOC(system on chip) often require a multi-clock design style for functional or performance reasons. The problems of the clock domain transition due to clock skew and clock ordering within a test cycle may result in wrong results. This paper describes a new BIST(Built-in Self Test) architecture for multi-clock systems. In the new scheme, a clock skew is eliminated by a multi-capture. Therfore, it is possible to perform at-speed test for both clock inter-domain and clock intra-domain.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.10
• /
• pp.2218-2226
• /
• 2009

TDMA based MAC protocol supporting wireless mesh network has many advantage rather than 802.11 DCF/EDCA protocol based on packet. But TDMA based MAC protocol require new synchronization method because of mobile point oscillator's difference, and distributed environments. This thesis propose synchronization method for TDMA based MAC protocol. It divides MP(Mobile Points) states into 4 types. If MP is in sync mode, it schedules TDMA local start time in time skew interval using beacon. It proposes compensation algorithms to compensate time skew caused by clock drift. This proposal show that general time error and clock drift rate value reduced and get synchronized result.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.1
• /
• pp.45-48
• /
• 2010

An inter-pin skew compensation scheme is proposed, which minimizes the inter-pin skew of parallel interface induced by unequal trace length and loading of printed circuit board (PCB). The proposed scheme measures the inter-pin skew and compensates during power-up with simple hardware. The proposed scheme is applied to 3.2-Gb/s/pin DDR4 SDRAM and implemented in a 0.18 m CMOS process. The inter-pin skew is compensated in 324-cycles of 400-MHz clock and the skew is compensated to be less than 24-ps.