• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.45 no.7
• /
• pp.1-8
• /
• 2008

Low Density Parity Check codes(LDPC) are recently focused on communication systems due to its good performance. The standard of WiBro has also included LDPC codes as a channel coding. The weak point of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which limit throughput. In this paper, we propose semi-parallel architecture by using cyclic shift registers and exclusive-OR without conventional Matrix Vector Multipliers over the standard parity check matrices with Circulant Permutation Matrices(CPM). Furthermore, multi-rate encoder is designed by using proposed architecture. Our encoder with multi-rate for IEEE 802.16e LDPC has lower clock cycles and higher throughput.

• BMB Reports
• /
• v.48 no.12
• /
• pp.677-684
• /
• 2015

Cardiovascular function is regulated by the rhythmicity of circadian, infradian and ultradian clocks. Specific time scales of different cell types drive their functions: circadian gene regulation at hours scale, activation-inactivation cycles of ion channels at millisecond scales, the heart's beating rate at hundreds of millisecond scales, and low frequency autonomic signaling at cycles of tens of seconds. Heart rate and rhythm are modulated by a hierarchical clock system: autonomic signaling from the brain releases neurotransmitters from the vagus and sympathetic nerves to the heart's pacemaker cells and activate receptors on the cell. These receptors activating ultradian clock functions embedded within pacemaker cells include sarcoplasmic reticulum rhythmic spontaneous Ca²⁺ cycling, rhythmic ion channel current activation and inactivation, and rhythmic oscillatory mitochondria ATP production. Here we summarize the evidence that intrinsic pacemaker cell mechanisms are the end effector of the hierarchical brain-heart circadian clock system.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.83-86
• /
• 2000

This paper describes a delay-locked loop(DLL_) with low-jitter using Vernier Method. This DLL can be used to synchronize the internal clock to the external clock with very short time interval and fast lock-on. The proposed circuit was simulated in a 0.25 $\mu\textrm{m}$ CMOS technology to realize low-jitter. We verified 50-ps of time interval within 5 clock cycles of the clock as the simulation results.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.711-714
• /
• 2005

We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.865-868
• /
• 2005

This paper presents a Clock-gating technique that reduces power dissipation of the sequential circuits in the system. The Master Clock of a Clock-gating technique is formed by a quaternary variable. It uses the covering relationship between the triggering transition of the clock and the active cycles of various flip-flops to generate a slave clock for each flip-flop in the circuit. At current RTL designs flip-flop is acted by Master clock's triggering but the Slave Clock of Clock-gating technique doesn't occur trigger when external input conditions have not matched with a condition of logic table. We have applied our clocking technique to UART controller of 8bit microprocess

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.3C
• /
• pp.256-262
• /
• 2002

This paper presents a novel radix-4 modular multiplication algorithm based on the sign estimation technique (3). The sign estimation technique detects the sign of a number represented in the form of a carry-sum pair. It can be implemented with 5-bit carry look-ahead adder. The hardware speed of the cryptosystem is dependent on the performance modular multiplication of large numbers. Our algorithm requires only (n/2+3) clock cycle for n bit modulus in performing modular multiplication. Our algorithm out-performs existing algorithm in terms of required clock cycles by a half, It is efficient for modular exponentiation with large modulus used in RSA cryptosystem. Also, we use high-speed adder (7) instead of CPA (Carry Propagation Adder) for modular multiplication hardware performance in fecal stage of CSA (Carry Save Adder) output. We apply RL (Right-and-Left) binary method for modular exponentiation because the number of clock cycles required to complete the modular exponentiation takes n cycles. Thus, One 1024-bit RSA operation can be done after n(n/2+3) clock cycles.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.12
• /
• pp.39-45
• /
• 2003

Design verification of VHDL models is getting difficult and has become a critical and time-consuming process in hardware design. Recent]y the methods using Bayesian estimation and stopping rule have been introduced to verify behavioral models and to reduce clock cycles. This paper presents two strategies to reduce clock cycles when using stopping rule in a VHDL model verification. The first method is that a semi-random variable is defined and the data that stay in the range of semi-random variable are skipped when stopping rule is running. The second one is to keep the old values of parameters when phases of stopping rule are changed. 12 VHDL models are examined to observe the effectiveness of strategies, and the simulation results show that more than about 25% of clock cycles is reduced by using the two proposed strategies with 0.6% losses of branch coverage rate.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.9 s.339
• /
• pp.29-34
• /
• 2005

This paper describes a novel internal clock generator, called duty cycle-corrected analog synchronous mirror delay (DCC-ASMD). The proposed circuit is well suited for dual edge-triggered systems such as double data-rate synchronous DRAM since it can achieve clock synchronization within two clock cycles with accurate duty cycle correction. To evaluate the performance of the proposed circuit, DCC-ASMD was designed using a $0.35\mu$m CMOS process technology. Simulation results show that the proposed circuit generates an internal clock having $50\%$ duty ratio within two clock cycles from the external clock having duty ratio range of $40\;\~\;60$.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.56 no.6
• /
• pp.1133-1138
• /
• 2007

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.

• Journal of Photoscience
• /
• v.9 no.2
• /
• pp.240-242
• /
• 2002

In Drosophila melanogaster, it is known that the circadian clock consists of an autoregulatory feedback loop, which includes so-called clock genes, such as per, tim, dClk and cyc and produces periodical expression of per. It is recently suggested, however, that the circadian oscillation without the rhythmical expression of per is involved in the regulation of circadian locomotor rhythms. In the present study, we examined the existence and the property of the possible per-less oscillation using arrhythmic clock mutant flies carrying per$^{01}$, tim$^{01}$, dClk$^{Jrk}$ or cyc$^{01}$. When temperature cycles consisting of 25$^{\circ}$Ｃ and 30$^{\circ}$Ｃ with varying periods (T = 8~32 hr) were given, they showed rhythms synchronizing with the given cycle under constant darkness (DD). per$^{01}$ and tim$^{01}$ flies always showed a peak around 7 hr after the onset of thermophase irrespective of Ts of temperature cycles, while dClk$^{Jrk}$ and cyc$^{01}$ flies did not. In addition, several days were necessary to establish a clear temperature entrainment in per$^{01}$ and tim$^{01}$ flies, when they were transferred from a constant temperature to a temperature cycle under DD. These results suggest that per$^{01}$ and tim$^{01}$ flies have a temperature-entrainable weak oscillatory mechanism. The fact that dClk$^{Jrk}$ and cyc$^{01}$ flies did not show any sign of the endogenous oscillation suggests that the per-less oscillatory mechanism may require CLK and CYC.