Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Efficient Methods for Reducing Clock Cycles in VHDL Model Verification

VHDL 모델 검증의 효율적인 시간단축 방법

  • Published : 2003.12.01
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Abstract

Design verification of VHDL models is getting difficult and has become a critical and time-consuming process in hardware design. Recent]y the methods using Bayesian estimation and stopping rule have been introduced to verify behavioral models and to reduce clock cycles. This paper presents two strategies to reduce clock cycles when using stopping rule in a VHDL model verification. The first method is that a semi-random variable is defined and the data that stay in the range of semi-random variable are skipped when stopping rule is running. The second one is to keep the old values of parameters when phases of stopping rule are changed. 12 VHDL models are examined to observe the effectiveness of strategies, and the simulation results show that more than about 25% of clock cycles is reduced by using the two proposed strategies with 0.6% losses of branch coverage rate.

칩의 크기가 증가함에 따라 VHDL 모델의 설계검증은 점점 어려워지고, 많은 시간을 소모하는 과정이 되고 있다. 최근에 VHDL 모델을 검증하기 위하여 베이지안 예측과 정지법(stopping rule)을 이용한 방법들이 소개되고 있다. 이 논문에서는 VHDL 모델을 검증하기 위하여 정지법을 사용할 때 클럭 사이클을 줄일 수 있는 2가지 방법을 제안한다. 첫 번째 방법은 세미랜덤변수를 정의하고, 정지법이 동작 중에 세미랜덤변수의 영역에 존재하는 데이터를 생략하여 정지점stopping point)을 줄이고, 두 번째 방법은 정지법의 페이즈가 변화시에 베이지안 파라미터의 기존 값을 그대고 유지하여 클럭 사이클을 줄이는 방법이다. 제안된 방법의 효율성을 입증하기 위하여 12개의 VHDL 모델에 대하여 분기검출율에 관한 모의실험을 하였으며, 기존의 방법과 비교하여 분기검출율은 0.6% 줄었지만 25% 이상의 클럭 사이클을 줄일 수 있었다.

Keywords

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