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Efficient Methods for Reducing Clock Cycles in VHDL Model Verification  

Kim, Kang-Chul (Computer Engineering, Yosu National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.12, 2003 , pp. 39-45 More about this Journal
Abstract
Design verification of VHDL models is getting difficult and has become a critical and time-consuming process in hardware design. Recent]y the methods using Bayesian estimation and stopping rule have been introduced to verify behavioral models and to reduce clock cycles. This paper presents two strategies to reduce clock cycles when using stopping rule in a VHDL model verification. The first method is that a semi-random variable is defined and the data that stay in the range of semi-random variable are skipped when stopping rule is running. The second one is to keep the old values of parameters when phases of stopping rule are changed. 12 VHDL models are examined to observe the effectiveness of strategies, and the simulation results show that more than about 25% of clock cycles is reduced by using the two proposed strategies with 0.6% losses of branch coverage rate.
Keywords
Verification; stopping rule; branch coverage; stopping point; semi-random variabl;
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1 A. Goel, 'Software reliability models: assump-tions, limitations, and application', IEEE transactions on software engineering, vSE -11,n 12, pp 1411-1423, Dec. 1985   DOI   ScienceOn
2 T. Chen, M. Sahinoglu, A. Mayrhauser, A. Hajjar, A Anderson, 'Achieving the quality for behavioral models with minimum effort', 1st international symposium on quality in electronic design, pp , Mar. 2000   DOI
3 Amjad Fuad A. Hajjar, 'Bayesian Based Stooping Rules for Behavioral VHDL Verification', Ph. D Dissertation, Fall 2000
4 M. Sahinoglu, A. Von Mayrhauser, A. Hajjar, T. Chen, C. Anderson, 'On the efficiency of a compound Poisson stopping rule for mixed strategy testing', IEEE Aerospace conference, Track 7, Mar. 1997   DOI
5 Jjm Lipman, 'Covering your HDL chip-design bets,' EDN, Oct. 22, 1998, pp 65-70
6 Brian Barrera, 'Code coverage analysis-essential to a safe design,' Electronic Engi-neering, pp 41-43, Nov. 1998
7 Kevin Skahill, 'A designer's guide to VHDL design and verification,' Engineering Software, pp 149-158, Feb. 1996
8 A. Von Mayrhauser, et. Al., 'On choosing test criteria for behavioral level hardware design verification', IEEE International Hign Level Design Validation and Test Workshop, Berkeley, CA, 2000   DOI
9 Janick Bergerson, Writing testbenches : func-tional verification of HDL model, Kluwer Academic, 2000
10 J. Gately, 'Verifying a million gate processor', Integrated System Design, pp 19-24, 1997
11 W. Howden, 'Confidence-based reliability and statistical coverage estimation', Proceedings on the international symposium on software reliability engineering, pp 283-291, Nov. 1997   DOI
12 G. Hayek, C. Robach, 'From specification validation to hardware testing: a unified met-hod', International Test conference, pp 885-893, 1996   DOI
13 S. Chen, S. Mills, 'A binary markov process model for random testing', IEEE transactions on software engineering, v22, n3, pp 218-223, Mar. 1996   DOI   ScienceOn
14 S. Surya, P. Bose, and J. Abraham, 'Architec-tural Performance Verification: PowerPC Processors', IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 344-347, Oct, 1994   DOI
15 R. Ramchandani, D. Thomas, 'Behavioral test generation using mixed integer nonlinear programming', International test conference, pp 958-967, 1994   DOI