Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2000.11b
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- Pages.83-86
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- 2000
Design of Low-jilter DLL using Vernier Method
Vernier 방법을 이용한 Low-jitter DLL 구현
Abstract
This paper describes a delay-locked loop(DLL_) with low-jitter using Vernier Method. This DLL can be used to synchronize the internal clock to the external clock with very short time interval and fast lock-on. The proposed circuit was simulated in a 0.25
Keywords