• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.1137-1140
• /
• 1999

In this thesis, we research about Communication System Construction and Test-Bed Realization Method and Software’s Design with written program into Embedded Micro Controller’s restricted memory region using a DSP Chip to deal with mainly high speed communication. Tools used for modern communication network control use TI or AMD general chip class, but nevertheless responsibility for the point at issue, Analog Device is architecture design model moderated for small communication system. In this thesis, we present extended model, and realize basic case.

• Proceedings of the KIEE Conference
• /
• 2004.07d
• /
• pp.2559-2561
• /
• 2004

This paper proposes the new signal-to-noise ratio(SNR) that is different from the conventional signal-to-noise ratio (SNR) in direct-sequence code-division multiple-access communication system employing offset quadrature phase-shift keying(OQPSK) and using a chip waveform. The conventional SNR value is so different from a real SNR value. Therefore, we propose a new SNR equation approximated to real SNR. The multiple-access interference(MAI) in DS-CDMA communication system has an effect on SNR performance and MAI is concerned with the correlation functions of the chip waveform. For this reason, we considered all possible correlations of chip waveforms. In conclusion, the SNR value of proposed method is enclosed to the real SNR value.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.11
• /
• pp.56-65
• /
• 2009

As increasing the number of IPs integrated in a single chip and requiring high communication bandwidth on a chip, the trend of SoC communication architecture is changed from bus- or crossbar-based architecture to packet switched network architecture, NoC. However, highly complex control logics in routers require multiple cycles to switch packet. In this paper, we design low complex router to improve the communication latency. Our NoC design is verified by simulation platform modeled by ESL tool, SoC Designer. We also evaluate our NoC design comparing to the previous NoC architecture based on VC router. Our results show that our NoC architecture has less communication latency, even small throughput degradation (about 1-2%).

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.11
• /
• pp.83-93
• /
• 2014

It is a widespread concern that electrical interconnection based network-on-chip (NoC) will ultimately face the limitation in communication bandwidth, transmission latency and power consumption in the near future. With the development of silicon photonics technology, a hybrid optical network-on-chip (HONoC) which embraces both electrical- and optical interconnect, is emerging as a promising solution to overcome these problems. Today's leading edge systems-on-chips (SoCs) comprise heterogeneous many-cores for higher energy efficiency, therefore, extended study beyond regular topology based NoC is required. This paper proposes an energy and latency optimization topology design technique for HONoC taking into account the traffic characteristics of target applications. The proposed technique is implemented with genetic algorithm and simulation results show the reduction by 13.84% in power loss and 28.14% in average latency, respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.1
• /
• pp.28-36
• /
• 2010

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.16 no.2
• /
• pp.97-104
• /
• 2011

This paper deals with the quick and precise disaster prevention automation system (DPAS) based on information communication technology (IT) that detects fire and disasters in the building automatically and quickly and then activates the facilities to extinguish fire and disasters, monitoring such situation in a real time through wire-wireless communication network. The proposed DPAS is applied a programmable logic controller (PLC) of one-chip type which is smallsize and lightweight and also has highly sensitive-precise reliabilities. The one-chip type PLC analyzes detected signals from sensors in a case of fire and disasters, then activates fire extinguishing facilities for rapid suppression. The detected data is also transferred to a remote situation room through wire-wireless network of RS232c and bluetooth communication. The transferred data sounds an emergency alarm signal, and operates a monitoring program. The proposed DPAS based on IT will minimize the life and wealth loss from rapid measures while prevents fire and disasters.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.6
• /
• pp.1282-1287
• /
• 2005

The accuracy of chip alignment in inferior product inspection of COG(Chip On Glass) to be measured a few micro unit is very important role since the accuracy of chip inspection depends on chip alignment. In this paper, we propose the area segmentation pattern matching method to enhance the accuracy of chip alignment. The area segmentation pattern matching method compares, and matches correlation coefficients between the characteristic features within the detailed area and the areas. The three areas of pattern circumference are learned to minimize the matching error by bad pattern. The proposed method has advantage such as reduction of matching time, and enhanced accuracy since the characteristic features are searched within the segmented area.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.5
• /
• pp.999-1008
• /
• 2012

Unlike the existing CMOS chip, ISB (Intelligent Silicon Bead) is new concept biochip equipped with optical communication and memory function. It uses the light for power of SoC CMOS and interface with external devices therefore it is possible to miniaturize a chip size and lower the cost. This paper introduces an input protocol and a design of the low power and the low area to transfer the power and the signal through a single optical signal applied from external reader device to bead chip at the same time. It is also verified through simulation and measurement. In addition, low-power PROM is designed for recording and storing ID of a chip and it is successful in obtaining the value of output according to the optical input. Through this study, a new type biochip development can be expected by solving high cost and a limit of miniaturizing a chip area problem of an existing RFID.

• Journal of IKEEE
• /
• v.18 no.4
• /
• pp.552-558
• /
• 2014

This paper suggests how to design a ZigBee-chip-based communication module to remotely measure radiation level. The suggested communication module consists of two control processors for the chip as generally required to configure a ZigBee system, and one chip module to configure a ZigBee RF device. The ZigBee-chip-based communication module for remote radiation measurement consists of a wireless communication controller; sensor and high-voltage generator; charger and power supply circuit; wired communication part; and RF circuit and antenna. The wireless communication controller is to control wireless communication for ZigBee and to measure radiation level remotely. The sensor and high-voltage generator generates 500 V in two consecutive series to amplify and filter pulses of radiation detected by G-M Tube. The charger and power supply circuit part is to charge lithium-ion battery and supply power to one-chip processors. The wired communication part serves as a RS-485/422 interface to enable USB interface and wired remote communication for interfacing with PC and debugging. RF circuit and antenna applies an RLC passive component for chip antenna to configure BALUN and antenna impedance matching circuit, allowing wireless communication. After configuring the ZigBee-chip-based communication module, tests were conducted to measure radiation level remotely: data were successfully transmitted in 10-meter and 100-meter distances, measuring radiation level in a remote condition. The communication module allows an environment where radiation level can be remotely measured in an economically beneficial way as it not only consumes less electricity but also costs less. By securing linearity of a radiation measuring device and by minimizing the device itself, it is possible to set up an environment where radiation can be measured in a reliable manner, and radiation level is monitored real-time.

• Molecules and Cells
• /
• v.45 no.2
• /
• pp.76-83
• /
• 2022

Neurons-on-a-Chip technology has been developed to provide diverse in vitro neuro-tools to study neuritogenesis, synaptogensis, axon guidance, and network dynamics. The two core enabling technologies are soft-lithography and microelectrode array technology. Soft lithography technology made it possible to fabricate microstamps and microfluidic channel devices with a simple replica molding method in a biological laboratory and innovatively reduced the turn-around time from assay design to chip fabrication, facilitating various experimental designs. To control nerve cell behaviors at the single cell level via chemical cues, surface biofunctionalization methods and micropatterning techniques were developed. Microelectrode chip technology, which provides a functional readout by measuring the electrophysiological signals from individual neurons, has become a popular platform to investigate neural information processing in networks. Due to these key advances, it is possible to study the relationship between the network structure and functions, and they have opened a new era of neurobiology and will become standard tools in the near future.