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http://dx.doi.org/10.5573/ieie.2014.51.11.083

Topology Design for Energy/Latency Optimized Application-specific Hybrid Optical Network-on-Chip (HONoC)  

Cui, Di (College of Information & Communication Engineering, Sungkyunkwan University)
Lee, Jae Hoon (College of Information & Communication Engineering, Sungkyunkwan University)
Kim, Hyun Joong (College of Information & Communication Engineering, Sungkyunkwan University)
Han, Tae Hee (College of Information & Communication Engineering, Sungkyunkwan University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.11, 2014 , pp. 83-93 More about this Journal
Abstract
It is a widespread concern that electrical interconnection based network-on-chip (NoC) will ultimately face the limitation in communication bandwidth, transmission latency and power consumption in the near future. With the development of silicon photonics technology, a hybrid optical network-on-chip (HONoC) which embraces both electrical- and optical interconnect, is emerging as a promising solution to overcome these problems. Today's leading edge systems-on-chips (SoCs) comprise heterogeneous many-cores for higher energy efficiency, therefore, extended study beyond regular topology based NoC is required. This paper proposes an energy and latency optimization topology design technique for HONoC taking into account the traffic characteristics of target applications. The proposed technique is implemented with genetic algorithm and simulation results show the reduction by 13.84% in power loss and 28.14% in average latency, respectively.
Keywords
HONoC; Topology design; Application-specific; Genetic algorithm;
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Times Cited By KSCI : 1  (Citation Analysis)
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