• ETRI Journal
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• 제32권1호
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• pp.68-72
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• 2010

The coupling between the transverse and longitudinal components of the channel electron motion in NMOS devices leads to a reduction in the barrier height. Therefore, this study theoretically investigates the effects of the in-plane velocity of channel electrons on the capacitance-voltage characteristics of nano NMOS devices under inversion bias. Numerical calculation via a self-consistent solution to the coupled Schrodinger equation and Poisson equation is used in the investigation. The results demonstrate that such a coupling largely affects capacitance-voltage characteristic when the in-plane velocity of channel electrons is high. The ballistic transport ensures a high in-plane momentum. It suggests that such a coupling should be considered in the quantum capacitance-voltage modeling in ballistic transport devices.

• E2M - 전기 전자와 첨단 소재
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• 제8권1호
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• pp.56-63
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• 1995

MESFETs of the Ti/Au and Ti/Pd/Au gate were fabricated on n-type GaAs. Interdiffusion at Schottky interfaces, Schottky contact properties, and MESFET characteristics with heat treatment were investigated. Ti of Ti/Au contact and Pd of Ti/Pd/Au contact acted as a barrier metal against interdiffusion of Au at >$220^{\circ}C$. Pd of Ti/Pd/Au contact acted as a barrier metal even at >$360^{\circ}C$, however, Ti of Ti/Au contact promoted interdiffusion of Au instead of role of barrier metal. As the heat treatment temperature increases, in the case of both contact, saturated drain current and pinch off voltage decreased, open channel resistance increased, and degree of parameter variation in Ti/Au gate was higher than in Ti/Pd/Au gate at >$360^{\circ}C$ Schottky barrier height of Ti/Au and Ti/Pd/Au contacts was 0.69eV and 0.68eV in the as-deposited state, respectively, and Fermi level was pinned in the vicinity of 1/2Eg. As the heat treatment temperature increases, barrier height of Ti/Pd/Au contact increased, however, decreased at >$360^{\circ}C$ in the case of Ti/Au contact. Ideality factor of Ti/Au contact was nearly constant regardless of heat treatment, however, increased at >$360^{\circ}C$ in the case of Ti/Au contact. From the results above, Ti/Pd/Au was stable gate metal than Ti/Au.

• 조명전기설비학회논문지
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• 제17권6호
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• pp.147-153
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• 2003

본 논문에서는 외부에 위치하는 소음원에 의하여, 창문 등과 같이 부분적인 개구부를 가지는 실내 공간에 소음이 전파될 때, 적응필터를 이용하여 이를 제어하는 능동 방음벽을 구현하였다. 적응필터의 수렴성을 증가시키기 위하여 다중채널 leaky LMS 알고리즘을 사용하였으며 창문 등의 개구부를 통하여 들어오는 소음을 제거하기 위하여 새로운 형태의 능동방음벽을 제안하였다. 기존의 ANC 기법을 이용한 기법과 제안한 기법을 TMS320C33 DSP를 이용한 실험을 통해 비교 분석하였다. 오차 마이크로폰의 위치에서는 ANB가 다소 좋은 결과를 얻었으나 두 경우 모두 비교적 좋은 결과를 얻을 수 있었지만, 전체 위치에서 소음의 감쇄를 소음계를 이용해 측정한 결과 ANB가 훨씬 좋은 결과를 보였다. ANC의 경우 보일러 소음의 경우는 평균적으로 차이가 거의 없었으며 위치에 따라서는 증가하는 곳도 있었으나, ANB의 경우는 단일 소음 및 보일러 소음 모두 증가하는 곳은 한 곳도 없었으며 평균적으로도 ANC의 경우보다 훨씬 좋은 결과를 보였다.

• 한국정보통신학회논문지
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• 제16권9호
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• pp.2015-2020
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• 2012

본 연구에서는 이중게이트(Double Gate; DG) MOSFET에 스켈링이론을 적용할 때 두 개의 게이트에 의한 효과를 반영하기 위하여 스켈링인자에 가중치를 적용하여 문턱전압이하 특성을 해석하였다. 포아송방정식에 의한 전위분포를 구하기 위하여 전하분포는 가우스분포함수를 이용할 것이며 이의 타당성은 이미 여러 논문에서 입증하였다. 이 전위분포를 이용하여 단채널효과 중 문턱전압이동, 문턱전압이하 스윙, 드레인유도장벽감소 등을 스켈링인자에 대한 가중치의 변화에 따라 관찰하였다. 이중게이트 MOSFET의 구조적 특성상 채널길이에 대한 가중치는 0.1에서 1까지 사용하였으며 채널두께에 대한 가중치는 1에서 2까지 가중치를 사용하였다. 결과적으로 문턱전압 이하 스윙은 스켈링인자에 따라 거의 변화가 없었으나 가중치에 따라 변화하였으며 문턱전압이동 및 드레인유도 장벽감소 등은 스켈링인자에 따라 그리고 가중치에 따라 큰 변화를 보이는 것을 알 수 있었다.

• 전기학회논문지
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• 제63권1호
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• pp.80-84
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• 2014

The discharge characteristics of Surface Dielectric Barrier Discharge (SDBD) reactor are investigated to find optimal driving condition with adjusting various parameter. When the high voltage with sine wave form is applied to SDBD source, successive pulsed current waveforms are observed owing to multiple ignitions through the long discharge channel and wall charge accumulation on the dielectric surface. The discharge voltage, total charge between dielectrics, mean energy and power are calculated from measured current and voltage according to electrode gap and dielectric thickness. Discharge mode transition from filamentary to diffusive glow is observed for narrow gap and high applied voltage case. However, when the diffusive discharge is occurred with high applied voltage, the actual firing voltage is always lower than that with low driving voltage. The $Si_3N_4$, $MgF_2$, $Al_2O_3$ and $TiO_2$ are considered for dielectric protection and high secondary electron emission coefficient. SDBD with $MgF_2$ shows the lowest breakdown voltage. $MgF_2$ thin film is proposed as a protection layer for low voltage atmospheric dielectric barrier discharge devices.

• 센서학회지
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• 제31권4호
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• pp.271-277
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• 2022

We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the N_it distribution using TCAD simulation. As interface trap number density (N_it) increased, the threshold voltage increased while the drain current density decreased. Under N_it=5.0×10¹⁰ cm^-2 condition, the threshold voltage was 3.2 V for V_DS=1 V, and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the N_it distribution type, there was an increase in the subthreshold swing (SS) following an increase in N_it. Under U-shaped N_it distribution, it was confirmed that the SS varied depending on the gate voltage. The interface fixed charge (Q_f) caused an shift in the threshold voltage and increased the off-state current collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectronic circuit provided the surface state is significantly reduced.

• Journal of Electrical Engineering and Technology
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• 제1권3호
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• pp.396-405
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• 2006

The visual analysis of buried channel (Be) devices such as buried channel MOSFETs and CCDs (Charge Coupled Devices) is investigated to give better understanding and insight for their electrical behaviours using a 3-dimensional (3-D) numerical simulation. This paper clearly demonstrates the capability of the numerical simulation of 'EVEREST' for characterising the analysis of a depletion mode MOSFET and BC CCD, which is a simulation software package of the semiconductor device. The inverse threshold and punch-through voltages obtained from the simulations showed an excellent agreement with those from the measurement involving errors of within approximately 1.8% and 6%, respectively, leading to the channel implanted doping profile of only approximately $4{\sim}5%$ error. For simulation of a buried channel CCD an advanced adaptive discretising technique was used to provide more accurate analysis for the potential barrier height between two channels and depletion depth of a deep depletion CCD, thereby reducing the CPU running time and computer storage requirements. The simulated result for the depletion depth also showed good agreement with the measurement. Thus, the results obtained from this simulation can be employed as the input data of a circuit simulator.

• Journal of Electrical Engineering and information Science
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• 제3권2호
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• pp.261-266
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• 1998

This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

• 한국전기전자재료학회논문지
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• 제24권2호
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• pp.152-155
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• 2011

Even though nano-scale materials were very advantageous for various applications, there are still problems to be solved such as the stabilization of surface state and realization of low contact resistances between a semiconducting nanowire and electrodes in nano-electronics. It is well known that the effects of contacts barrier between nano-channel and metal electrodes were dominant in carrier transportation in individual nano-electronics. In this report, it was investigated the electrical properties of GaN nanorod devices after chemical etching and rapid thermal annealing for making good contacts. After KOH wet-etching of the contact area the devices showed better electrical performance compared with non-treated GaN individual devices but still didn't have linear voltage-current characteristics. The shape of voltage-current properties of GaN devices were improved remarkably after rapid thermal annealing as showing Ohmic behaviors with further bigger conductivities. Even though chemical etching of the nanorod surfaces could cause scattering of carriers, in here it was shown that the most important and dominant factor in carrier transport of nano-electronics was realization of low contact barrier between nano-channel and metal electrodes surely.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.357-357
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• 2008

에피성장된 Fe/GaAs 적층구조에서의 스핀 주입 실험을 하였다. Fe와 GaAs 사이에 Schottky tunnel barrier를 형성시키기 위하여 높게 도핑된 GaAs 층을 channel 층 위에 성장하였다. 스핀전달에 의한 chemical potential 차이만을 검출하기 위해서 전압 측정 단자 사이에 전류 흐름이 포함되지 않는 non-local 측정방법을 사용하였다. 그 결과 두 강자성 전극이 반평행한 구간에서 dip이 나타나는 것을 확인할 수 있었다.