• Title/Summary/Keyword: capacitor voltage

Search Result 1,824, Processing Time 0.03 seconds

Optimization of highly scalable gate dielectrics by stacking Ta2O5 and SiO2 thin films for advanced MOSFET technology

  • Kim, Tae-Wan;Jo, Won-Ju
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2016.02a
    • /
    • pp.259-259
    • /
    • 2016
  • 반도체 산업 전반에 걸쳐 이루어지고 있는 연구는 소자를 더 작게 만들면서도 구동능력은 우수한 소자를 만들어내는 것이라고 할 수 있다. 따라서 소자의 미세화와 함께 트랜지스터의 구동능력의 향상을 위한 기술개발에 대한 필요성이 점차 커지고 있으며, 고유전(high-k)재료를 트랜지스터의 게이트 절연막으로 이용하는 방법이 개발되고 있다. High-k 재료를 트랜지스터의 게이트 절연막에 적용하면 낮은 전압으로 소자를 구동할 수 있어서 소비전력이 감소하고 소자의 미세화 측면에서도 매우 유리하다. 그러나, 초미세화된 소자를 제작하기 위하여 high-k 절연막의 두께를 줄이게 되면, 전기적 용량(capacitance)은 커지지만 에너지 밴드 오프셋(band-offset)이 기존의 실리콘 산화막(SiO2)보다 작고 또한 열공정에 의해 쉽게 결정화가 이루어지기 때문에 누설전류가 발생하여 소자의 열화를 초래할 수 있다. 따라서, 최근에는 이러한 문제를 해결하기 위하여 게이트 절연막 엔지니어링을 통해서 누설전류를 줄이면서 전기적 용량을 확보할 수 있는 연구가 주목받고 있다. 본 실험에서는 high-k 물질인 Ta2O5와 SiO2를 적층시켜서 누설전류를 줄이면서 동시에 높은 캐패시턴스를 달성할 수 있는 게이트 절연막 엔지니어링에 대한 연구를 진행하였다. 먼저 n-type Si 기판을 표준 RCA 세정한 다음, RF sputter를 사용하여 두께가 Ta2O5/SiO2 = 50/0, 50/5, 50/10, 25/10, 25/5 nm인 적층구조의 게이트 절연막을 형성하였다. 다음으로 Al 게이트 전극을 150 nm의 두께로 증착한 다음, 전기적 특성 개선을 위하여 furnace N2 분위기에서 $400^{\circ}C$로 30분간 후속 열처리를 진행하여 MOS capacitor 소자를 제작하였고, I-V 및 C-V 측정을 통하여 형성된 게이트 절연막의 전기적 특성을 평가하였다. 그 결과, Ta2O5/SiO2 = 50/0, 50/5, 50/10 nm인 게이트 절연막들은 누설전류는 낮지만, 큰 용량을 얻을 수 없었다. 한편, Ta2O5/SiO2 = 25/10, 25/5 nm의 조합에서는 충분한 용량을 확보할 수 있었다. 적층된 게이트 절연막의 유전상수는 25/5 nm, 25/10 nm 각각 8.3, 7.6으로 비슷하였지만, 문턱치 전압(VTH)은 각각 -0.64 V, -0.18 V로 25/10 nm가 0 V에 보다 근접한 값을 나타내었다. 한편, 누설전류는 25/10 nm가 25/5 nm보다 약 20 nA (@5 V) 낮은 것을 확인할 수 있었으며 절연파괴전압(breakdown voltage)도 증가한 것을 확인하였다. 결론적으로 Ta2O5/SiO2 적층 절연막의 두께가 25nm/10nm에서 최적의 특성을 얻을 수 있었으며, 본 실험과 같이 게이트 절연막 엔지니어링을 통하여 효과적으로 누설전류를 줄이고 게이트 용량을 증가시킴으로써 고집적화된 소자의 제작에 유용한 기술로 기대된다.

  • PDF

A 14b 150MS/s 140mW $2.0mm^2$ 0.13um CMOS ADC for SDR (Software Defined Radio 시스템을 위한 14비트 150MS/s 140mW $2.0mm^2$ 0.13um CMOS A/D 변환기)

  • Yoo, Pil-Seon;Kim, Cha-Dong;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.4
    • /
    • pp.27-35
    • /
    • 2008
  • This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

High Efficiency Triple Mode Boost DC-DC Converter Using Pulse-Width Modulation (펄스폭 변조를 이용한 고효율 삼중 모드 부스트 변환기)

  • Lee, Seunghyeong;Han, Sangwoo;Kim, Jongsun
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.52 no.2
    • /
    • pp.89-96
    • /
    • 2015
  • This paper presents a high efficiency, PSM/DCM/CCM triple mode boost DC-DC converter for mobile application. This device operates at Pulse-Skipping Mode(PSM) when it enters light load, and otherwise operate the operating frequency of 1.4MHz with Pulse-Width Modulation(PWM) mode. Especially in order to improve the efficiency during the Discontinuous-Conduction Mode(DCM) operation period, the reverse current prevention circuit and oscillations caused by the inductor and the parasitic capacitor to prevent the Ringing killer circuit is added. The input voltage of the boost converter ranges from 2.5V ~ 4.2V and it generates the output of 4.8V. The measurement results show that the boost converter provides a peak efficiency of 92% on CCM and 87% on DCM. And an efficiency-improving PWM operation raises the efficiency drop because of transition from PWM to PFM. The converter has been fabricated with a 0.18um Dongbu BCDMOS technology.

Electrode Dependence of Asymmetric Behavior of (La,Sr)CoO₃/Pb(Zr,Ti)O₃/(La,Sr)CoO₃ Thin Film Capacitors ((La,Sr)CoO₃/Pb(Zr,Ti)O₃/(La,Sr)CoO₃박막 캐패시터의 비대칭성의 전극 의존성)

  • 최치홍;이재찬;박배호;노태원
    • Journal of the Korean Ceramic Society
    • /
    • v.35 no.7
    • /
    • pp.647-647
    • /
    • 1998
  • (La,Sr)CoO3/Pb(Zr,Ti)O3/(La,Sr)CoO3 (LSCO) heterostructures have been grown on LaAlO3 substrates by pulsed laser deposition (PLD) to investigate asymmetric polarization of Pb(Zr,Ti)O3 (PZT) thin flims with different electrode configuration. P-V hysteresis loop of LSCO/PZT/LSCO was symmetric. However, LaCoO3 (LCO_/PZT/LSCO showed a largely asymmetric P-V hystersis loop and large relaxation of the remanent polarization at the negatively poled state, which means that the negatively poled state was unstable. On the other hand, LSCO/PZT/LCO exhibited large relaxation of the positively poled state. The asymmetric behavior of the polarized states implies the presence of an interal electric firld inside the PZT layer. It is suggested that internal electric field is caused by built-in voltages at LCO/PZT and LSCO/PZT interfaces. The built-in voltages at LCO/PZT and CSCO/PZT interfaces were 0.6 V and -0.12 V, respectively.

Third order Sigma-Delta Modulator with Delayed Feed-forward Path for Low-power Operation (저전력 동작을 위한 지연된 피드-포워드 경로를 갖는 3차 시그마-델타 변조기)

  • Lee, Minwoong;Lee, Jongyeol
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.51 no.10
    • /
    • pp.57-63
    • /
    • 2014
  • This paper proposes an architecture of $3^{rd}$ order SDM(Sigma-Delta Modulator) with delayed feed-forward path in order to reduce the power consumption and area. The proposed SDM improve the architecture of conventional $3^{rd}$ order SDM which consists of two integrators. The proposed architecture can increase the coefficient values of first stage doubly by inserting the delayed feed-forward path. Accordingly, compared with the conventional architecture, the capacitor value($C_I$) of first integrator is reduced by half. Thus, because the load capacitance of first integrator became the half of original value, the output current of first op-amp is reduced as 51% and the capacitance area of first integrator is reduced as 48%. Therefore, the proposed method can optimize the power and the area. The proposed architecture in this paper is simulated under conditions which are supply voltage of 1.8V, input signal 1Vpp/1KHz, signal bandwidth of 24KHz and sampling frequency of 2.8224MHz in the 0.18um CMOS process. The simulation results are SNR(Signal to Noise Ratio) of 88.9dB and ENOB(Effective Number of Bits) of 14-bits. The total power consumption of the proposed SDM is $180{\mu}W$.

Design of Low Power 4th order ΣΔ Modulator with Single Reconfigurable Amplifier (재구성가능 연산증폭기를 사용한 저전력 4차 델타-시그마 변조기 설계)

  • Sung, Jae-Hyeon;Lee, Dong-Hyun;Yoon, Kwang Sub
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.54 no.5
    • /
    • pp.24-32
    • /
    • 2017
  • In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

The Fabrication of OTFT-OLED Array Using Ag-paste for Source and Drain Electrode (Ag 페이스트를 소스와 드레인 전극으로 사용한 OTFT-OLED 어레이 제작)

  • Ryu, Gi-Seong;Kim, Young-Bae;Song, Chung-Kun
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.5
    • /
    • pp.12-18
    • /
    • 2008
  • Ag paste was employed for source and drain electrode of OTFTs and for the data metal lines of OTFT-OLED array on PC(polycarbonate) substrate. We tested two kinds of Ag-pastes such as pastes for 325 mesh and 500 mesh screen mask to examine the pattern ability and electrical performance for OTFTs. The minimum feature size was 60 ${\mu}m$ for 325 mesh screen mask and 40 ${\mu}m$ for 500 mesh screen mask. The conductivity was 60 $m{\Omega}/\square$ for 325 mesh and 133.1 $m{\Omega}/\square$ for 500 mesh. For the OTFT performance the mobility was 0.35 $cm^2/V{\cdot}sec$ and 0.12 $cm^2/V{\cdot}sec$, threshold voltage was -4.7 V and 0.9 V, respectively, and on/off current ratio was ${\sim}10^5$, for both screen masks. We applied the 500 mash Ag paste to OTFT-OLED array because of its good patterning property. The pixel was composed of two OTFTs and one capacitor and one OLED in the area of $2mm{\times}2mm$. The panel successfully worked in active mode operation even though there were a few bad pixels.

A Re-configurable 0.8V 10b 60MS/s 19.2mW 0.13um CMOS ADC Operating down to 0.5V (0.5V까지 재구성 가능한 0.8V 10비트 60MS/s 19.2mW 0.13um CMOS A/D 변환기)

  • Lee, Se-Won;Yoo, Si-Wook;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.3
    • /
    • pp.60-68
    • /
    • 2008
  • This work describes a re-configurable 10MS/s to 100MS/s, low-power 10b two-step pipeline ADC operating at a power supply from 0.5V to 1.2V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10b accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the MDAC while a switched-bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB. The ADC with an active die area of $0.98mm^2$ shows a maximum SNDR and SFDR of 56.0dB and 69.6dB, respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V and 60MS/s.

A 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for High-Quality Video Systems (고화질 영상 시스템 응용을 위한 12비트 130MS/s 108mW $1.8mm^2$ 0.18um CMOS A/D 변환기)

  • Han, Jae-Yeol;Kim, Young-Ju;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.3
    • /
    • pp.77-85
    • /
    • 2008
  • This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

Synthesis of Nitrogen-Doped Porous Carbon Fibers Derived from Coffee Waste and Their Electrochemical Application (커피 폐기물 기반의 질소가 포함된 다공성 탄소 섬유의 제조 및 전기화학적 응용)

  • Dong Hyun Kim;Min Sang Kim;Suk Jekal;Jiwon Kim;Ha-Yeong Kim;Yeon-Ryong Chu;Chan-Gyo Kim;Hyung Sub Sim;Chang-Min Yoon
    • Journal of the Korea Organic Resources Recycling Association
    • /
    • v.31 no.1
    • /
    • pp.57-68
    • /
    • 2023
  • In this study, coffee waste was recycled into nitrogen-doped porous carbon fibers as an active material for high-energy EDLC (Electric Double Layer Capacitors). The coffee waste was mixed with polyvinylpyrrolidone and dissolved into dimethylformamide. The mixture was then electrospun to fabricate coffee waste-derived nanofibers (Bare-CWNF), and carbonization process was followed under a nitrogen atmosphere at 900℃. Similar to Bare-CWNF, the as-synthesized carbonized coffee waste-derived nanofibers (Carbonized-CWNF) maintained its fibrous form while preserving the composition of nitrogen. The electrochemical performance was analyzed for carbonized coffee waste (Carbonized-CW)-, carbonized PAN-derived nanofibers (Carbonized-PNF)-, and Carbonized-CWNF-based electrodes in the operating voltage window of -1.0-0.0V, Among the electrodes, Carbonized-CWNF-based electrodes exhibited the highest specific capacitance of 123.8F g-1 at 1A g-1 owing to presence of nitrogen and porous structure. As a result, nitrogen-contained porous carbon fibers synthesized from coffee waste showed excellent electrochemical performance as electrodes for high-energy EDLC. The experimental designed in this study successfully demonstrated the recycling of the coffee waste, one of the plant-based biomass that causes the environmental pollution into high-energy materials, also, attaining the ecofriendliness.