• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.99-102
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• 2003

Reactions between 48Sn-52In solder and under bump metallurgies(UBM) such as 100nm $Ti/8{\mu}m$ Cu and 300nm Al/400nm Ni(V)/400nm Cu have been investigated, and the shear strength of 48Sn-52In solder bumps on each UBM has been evaluated. While intermetallic compounds with two different morphologies were continuously thickened on Ti/Cu with repeating the reflow process, the intermetallics on Al/Ni(V)/Cu spalled into the solder with increasing the number of reflow times. The solder bumps on Ti/Cu exhibited higher shear strength than those on Al/Ni(V)/Cu.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.61-71
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• 1999

The recent trend toward higher frequencies, miniaturization and lower-cost in wireless communication equipment is demanding high density packaging technologies such flip chip interconnection and multichip module(MCM) as a substitute of conventional plastic package. With analyzing the recently reported research results of the RF flip chip, this paper presents the technical issues and advantages of RF flip chip and suggest the flip chip technologies suitable for the development stage. At first, most of RF flip chips are designed in a coplanar waveguide line instead of microstrip in order to achieve better electrical performance and to avoid the interaction with a substrate. Secondly, eliminating wafer back-side grinding, via formation, and back-side metallization enables the manufacturing cost to be reduced. Finally, the electrical performance of flip chip bonding is much better than that of plastic package and the flip chip interconnection is more suitable for Transmit/Receiver modules at higher frequency. However, the characterization of CPW designed RF flip chip must be thoroughly studied and the Au stud bump bonding shall be suggested at the earlier stage of RF flip chip development.

• Journal of Welding and Joining
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• v.29 no.6
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• pp.65-70
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• 2011

The effect of flip chip bonding parameters on formation of intermetallic compounds (IMCs) between Au stud bumps and Sn-3.5Ag solder was investigated. In this study, flip chip bonding temperature was performed at $260^{\circ}C$ and $300^{\circ}C$ with various bonding times of 5, 10, and 20 sec. AuSn, $AuSn_2$ and $AuSn_4$ IMCs were formed at the interface of joints and (Au, Cu)$_6Sn_5$ IMC was observed near Cu pad side in the joint. At bonding temperature of $260^{\circ}C$, $AuSn_4$ IMC was dominant in the joint compared to other Au-Sn IMCs as bonding time increased. At bonding temperature of $300^{\circ}C$, $AuSn_2$ IMC clusters, which were surrounded by $AuSn_4$ IMC, were observed in the solder joint due to fast diffusivity of Au to molten solder with increased bonding temperature. Bond strength of Au stud bump joined with Sn-3.5Ag solder was about 23 gf/bump and fracture mode of the joint was intergranular fracture between $AuSn_2$ and $AuSn_4$ IMCs regardless bonding conditions.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.111-119
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• 2005

Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

• Journal of the Semiconductor & Display Technology
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• v.15 no.4
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• pp.10-15
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• 2016

In this paper, novel ball grid array (BGA) interconnection process using solderable anisotropic conductive adhesives (SACAs) with low-melting-point alloy (LMPA) fillers have been developed to enhance the processability in the conventional capillary underfill technique and to overcome the limitations in the no-flow underfill technique. To confirm the feasibility of the proposed technique, BGA interconnection test was performed using two types of SACA with different LMPA concentration (0 and 4 vol%). After the interconnection process, the interconnection characteristics such as morphology of conduction path and electrical properties of BGA assemblies were inspected and compared. The results indicated that BGA assemblies using SACA without LMPA fillers showed weak conduction path formation such as solder bump loss or short circuit formation because of the expansion of air bubbles within the interconnection area due to the relatively high reflow peak temperature. Meanwhile, assemblies using SACA with 4 vol% LMPAs showed stable metallurgical interconnection formation and electrical resistance due to the favorable selective wetting behavior of molten LMPAs for the solder bump and Cu metallization.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.95-103
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• 2005

The interfacial reaction between 42Sn-58Bi solder (in wt.$\%$ unless specified otherwise) and electroless Ni-P/immersion Au has been investigated before and after thermal aging, with a focus on formation and growth of an intermetallic compound (IMC) layer, consumption of under bump metallurgy (UBM), and bump shear strength. The immersion Au layer with thicknesses of 0 (bare Ni), 0.1, and $1{\mu}m$ was plated on the $5{\mu}m$ thick electroless Ni-P ($14{\~}15 at.\%$P) layer. Then, the 42Sn-58Bi solder balls were fabricated on three different UBM structures by screen-printing and pre-reflow. The $Ni_3Sn_4$ layer (IMC1) was formed at the joint interface after pre-reflow for all the three UBM structures. On aging at $125^{\circ}C$, a quaternary phase (IMC2) was observed above the $Ni_3Sn_4$ layer in the Au-containing UBM structures, which was identified as $Sn_{77}Ni{15}Bi_6Au_2$ (in at.$\%$). The thick $Sn_{77}Ni{15}Bi_6Au_2$ layer deteriorated the integrity of the solder joint and the shear strength of the solder bump was decreased by about $40\%$ compared with non-aged joints.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.4 s.33
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• pp.43-48
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• 2004

Electromigration of Sn-3.5Ag-0.5Cu solder bumps was investigated with current densities of $3{\~}4{\times}10^4 A/cm^2$ at temperatures of $130{\~}160^{\circ}C$ using flip chip specimens which consisted of upper Si chip and lower Si substrate. Electromigration failure of the Sn-3.5Ag-0.5Cu solder bump occurred with complete consumption of Cu UBM and void formation at cathode side of the solder bump. The activation energies for electromigration of the Sn-3.5Ag-0.5Cu solder bump were measured as 0.61 eV at current density of $3{\times}10^4 A/cm^2$, 0.63 eV at $3.5{\times}10^4 A/cm^2$, and 0.77 eV at $4{\times}10^4 A/cm^2$, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.366-369
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• 2003

The vertical fountain plating system with the point contact has been used in semiconductor industry. But the plating shape in the opening of photoresist becomes gradated shape, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. So, we designed the tilted electrode ring contact to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and $\alpha$-step. A photoresist was coated to a thickness of $60{\mu}m$ and vias were patterned by a contact aligner After via opening, solder layer was electroplated using the fountain plating system and the tilted electrode ring contact system. In $\alpha$-step measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were ${\pm}16%,\;{\pm}3.7%$ respectively. In this study, we could get high uniformity bumps by the tilted electrode ring contact system. So, tilted electrode ring contact system is expected to improve workability and yield in module process.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.2
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• pp.13-21
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• 1999

Flip chip assembly directly on organic boards offers miniaturization of package size as well as reduction in interconnection distances resulting in a high performance and cost-competitive Packaging method. This paper describes the investigation of alternative low cost flip-chip mounting processes using electroless Ni/Au bump and anisotropic conductive adhesives/films as an interconnection material on organic boards such as FR-4. As bumps for flip chip, electroless Ni/Au plating was performed and characterized in mechanical and metallurgical point of view. Effect of annealing on Ni bump characteristics informed that the formation of crystalline nickel with $Ni_3$P precipitation above $300^{\circ}C$ causes an increase of hardness and an increase of the intrinsic stress resulting in a reliability limitation. As an interconnection material, modified ACFs composed of nickel conductive fillers for electrical conductor and non-conductive inorganic fillers for modification of film properties such as coefficient of thermal expansion(CTE) and tensile strength were formulated for improved electrical and mechanical properties of ACF interconnection. The thermal fatigue life of ACA/F flip chip on organic board limited by the thermal expansion mismatch between the chip and the board could be increased by a modified ACA/F. Three ACF materials with different CTE values were prepared and bonded between Si chip and FR-4 board for the thermal strain measurement using moire interferometry. The thermal strain of ACF interconnection layer induced by temperature excursion of $80^{\circ}C$ was decreased with decreasing CTEs of ACF materials.

• ETRI Journal
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• v.35 no.4
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• pp.625-631
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• 2013

For the formation of solder bumps with a fine pitch of 130 ${\mu}m$ on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of $220^{\circ}C$. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 ${\mu}m$, 18.3 ${\mu}m$, and 12.0 ${\mu}m$, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.