• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.175-184
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• 2006

In this paper, we describe a 900MHz CMOS RF transceiver using an ISM band for ZigBee applications. The architecture of the designed rx front-end, which consists of a low noise amplifier, a down-mixer, a programmable gain amplifier and a band pass filter. And the tx front-end, which consists of a band pass filter, a programmable gain amplifier, an up-mixer and a drive amplifier. A low-if topology is adapted for transceiver architecture, and the total current consumption is reduced by using a low power topology. Entire transceiver is verified by means of post-layout simulation and is implemented in 0.18um RF CMOS technology. The fabricated chip demonstrate the measured results of -92dBm minimum rx input level and 0dBm maximum tx output level. Entire power consumption is 32mW(@1.8VDD). Die area is $2.3mm{\times}2.5mm$ including ESD protection diode pads.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.109-116
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• 2022

In this paper, we propose a band rejection filter (BRF) with a state variable filter (SVF) structure to effectively remove the influence of 60 Hz line frequency noise introduced into the sensor system. The conventional BRF of the SVF structure uses an additional operational amplifier (OPAMP) to add a low pass filter (LPF) output and a high pass filter (HPF) output or an input signal and a band pass filter. Therefore, the notch frequency and the notch depth that determine the signal attenuation of the BRF greatly depend on the tolerance of the resistors used to obtain the sum or difference of the signals. On the other hand, in the proposed BRF, since the BRF output is formed naturally within the SVF structure, there is no need for a combination between each port. The notch frequency of the proposed BRF is 59.99 Hz, and it can be confirmed that it is not affected at all by the tolerance of the resistor through the Monte Carlo simulation results. The notch depth also has an average of -42.54dB and a standard deviation of 0.63dB, confirming that normal operation as a BRF is possible. Also, with the proposed BRF, noise filtering was applied to the electrocardiogram (ECG) signal that interfered with 60 Hz noise, and it was confirmed that the 60 Hz noise was appropriately suppressed.

• The Journal of the Korea Contents Association
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• v.6 no.4
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• pp.1-10
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• 2006

In this paper, a broadband RF module is designed and tested for 2.4GHz band applications. The RF module is composed of a low noise amplifier (LNA) with a three stage amplifier, a single ended gate mixer, matching circuits, a hairpin line band pass filter and a Chebyshev low pass filter to convert the radio frequency (RF) into the intermediate frequency (IF). The LNA has a high gain and stability, and the single ended gate mixer has a high conversion gain and wide dynamic range. In the analysis of the broadband RF module, the composite harmonic balance technique is used to analyze the operating characteristics of an RF module circuit. The RF module has a 55.2dB conversion gain with a 1.54dB low noise figure, $-120{\sim}-60dBm$ wide RF power dynamic range, -60dBm low harmonic spectrum and a good isolation factor among the RF, IF, and local oscillator (LO) ports.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.282-291
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• 2010

This paper presents a full-CMOS transmitter and receiver for VDSL2 systems. The transmitter part consists of the low-pass filter, programmable gain amplifier (PGA) and 14-bit DAC. The receiver part consists of the low-pass filter, variable gain amplifier (VGA), and 13-bit ADC. The low pass filter and PGA are designed to support the variable data rate. The RC bank sharing architecture for the low pass filter has reduced the chip size significantly. And, the 80 Msps, high resolution DAC and ADC are integrated to guarantee the SNR. Also, the transmitter and receiver are designed to have a wide dynamic range and gain control range because the signal from the VDSL2 line is variable depending on the distance. The chip is implemented in 0.25 ${\mu}m$ CMOS technology and the die area is 5 mm $\times$ 5 mm. The spurious free dynamic range (SFDR) and SNR of the transmitter and receiver are 67.5 dB and 41 dB, respectively. The power consumption of the transmitter and receiver are 160 mW and 250 mW from the supply voltage of 2.5 V, respectively.

• ETRI Journal
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• v.28 no.4
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• pp.495-501
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• 2006

This paper presents a new CMOS fully-differential second-generation current conveyor (FDCCII). The proposed FDCCII is based on a fully-differential difference transconductor as an input stage and two class AB output stages. Besides the proposed FDCCII circuit operating at a supply voltage of ${\pm}1.5\;V$, it has a total standby current of $380\;{\mu}A$. The applications of the FDCCII to realize a variable gain amplifier, fully-differential integrator, and fully-differential second-order bandpass filter are given. The proposed FDCII and its applications are simulated using CMOS $0.35\;{\mu}m$ technology.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2733-2736
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• 2003

This paper proposes a dry-type active surface EMG electrode for the myoelectric prosthetic hand. The designed electrode is small size for embedding in the socket of prosthetic hand, and it has three leads including the reference of signal. To acquire EMG signal rejected the power noise, a precision differential amplifier and various filters such as the band pass filter band rejection filter, low pass and high pass filter are embedded on the electrode. The final output of the electrode is integrated absolute EMG (IEMG) obtained by full rectifier and moving average circuits. From experimental results using the implemented dry-type active surface EMG electrode, the proposed electrode is feasible for the myoelectric prosthetic hand.

• Journal of electromagnetic engineering and science
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• v.9 no.1
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• pp.7-11
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• 2009

An Ultra-WideBand(UWB) Low-Noise Amplifier(LNA) is proposed and is implemented in a $0.18-{\mu}m$ CMOS technology. The proposed UWB LNA provides excellent wideband characteristics by combining a High-Pass Filter (HPF) with a conventional resistive-loaded LNA topology. In the proposed UWB LNA, the bell-shaped gain curve of the overall amplifier is much less dependent on the frequency response of the HPF embedded in the input stage. In addition, the adoption of fewer on-chip inductors in the input matching network permits a lower noise figure and a smaller chip area. Measurement results show a power gain of + 10 dB and an input return loss of more than - 9 dB over 2.7 to 6.2 GHz, a noise figure of 3.1 dB at 3.6 GHz and 7.8 dB at 6.2 GHz, an input PldB of - 12 dBm, and an IIP3 of - 0.2 dBm, while dissipating only 4.6 mA from a 1.8-V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.5
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• pp.426-429
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• 2017

For the W-band remote sensing radiometer, direct detection type radiometer receiver is designed. The receiver should be low noise and high gain of 60 dB unlike communication and radar receiver. The W-band radiometer consist of 4-stage low noise, high gain amplifier, band pass filter and square law detector. The developed direct detection receiver show 4 GHz bandwidth, 56 dB gain, and 4,500 mV/mW voltage sensitivity at integrator output port for -20 dBm input power at 94 GHz.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1983.04a
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• pp.29-32
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• 1983

In order to design the simple and economic Band-Pass Active filter, 2nd-order BPF using OP-amplifier were studied by their experments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.92-97
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• 2009

Low power consumption is crucial for medical implantable devices. A low-power 4th-order band-pass Gm-C filter with distributed gain stage for the sensing stage of the implantable cardiac pacemaker is proposed. For the implementation of large-time constants, a floating-gate operational transconductance amplifier with current division is employed. Experimental results for the filter have shown a SFDR of 50 dB. The power consumption is below $1.8{\mu}W$, the power supply is 1.5 V, and the core area is $2.4\;mm{\times}1.3\;mm$. The filter was fabricated in a 1-poly 4-metal $0.35-{\mu}m$ CMOS process.