JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 67.5 dB SFDR Full-CMOS VDSL2 CPE Transmitter and Receiver with Multi-Band Low-Pass Filter

  • Park, Joon-Sung (Department of Electronic Engineering, Konkuk University) ;
  • Park, Hyung-Gu (Department of Electronic Engineering, Konkuk University) ;
  • Pu, Young-Gun (Department of Electronic Engineering, Konkuk University) ;
  • Lee, Kang-Yoon (Department of Electronic Engineering, Konkuk University)
  • Received : 2010.11.29
  • Published : 2010.12.31
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Abstract

This paper presents a full-CMOS transmitter and receiver for VDSL2 systems. The transmitter part consists of the low-pass filter, programmable gain amplifier (PGA) and 14-bit DAC. The receiver part consists of the low-pass filter, variable gain amplifier (VGA), and 13-bit ADC. The low pass filter and PGA are designed to support the variable data rate. The RC bank sharing architecture for the low pass filter has reduced the chip size significantly. And, the 80 Msps, high resolution DAC and ADC are integrated to guarantee the SNR. Also, the transmitter and receiver are designed to have a wide dynamic range and gain control range because the signal from the VDSL2 line is variable depending on the distance. The chip is implemented in 0.25 ${\mu}m$ CMOS technology and the die area is 5 mm $\times$ 5 mm. The spurious free dynamic range (SFDR) and SNR of the transmitter and receiver are 67.5 dB and 41 dB, respectively. The power consumption of the transmitter and receiver are 160 mW and 250 mW from the supply voltage of 2.5 V, respectively.

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References

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