• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.11
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• pp.2956-2979
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• 2012

Along with the development of Information Technology, online transactions through Internet have become more popular for the reasons of convenience and efficiency. In order to provide secure and reliable online transactions, an effective electronic payment protocol is crucial. In this paper, we propose a novel electronic payment protocol for digital product transactions with an offline arbiter to achieve fair exchange, automated dispute resolution, customer anonymity, and customer unlinkability. In our protocol a product token is adopted to eliminate the need of key management for digital product decryption in the offline arbiter. In addition, Elliptic Curve Cryptography (ECC)-based self-certified public key is utilized to further reduce computing overheads. According to our analysis, the efficiency of our protocol can be greatly increased in comparison with previous literatures.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.569-570
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• 2008

This paper proposed a new arbitration method in arbiter which is one of bus system components for the design of SoC. Considering compatibility between IP and bus system, the performance of bus system can change the performance of SoC chip. The proposed arbitration method achieved the performance improvement with high efficiency depending on the environment in use.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.38-44
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• 2009

Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method bus system performance can be charged definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this stuff, we proposed the score arbitration method and composed TLM algorithm. Also we analyze the performance compared with general arbitration methods through simulation. In the future, bus arbitration policy will be developed with the basis of the score arbitration method and improve the performance of bus system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.31-34
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• 2018

This paper presents a low-power buck-boost converter for multi-input energy harvesting systems. The designed circuit combines the energy harvested from three input channels in real time and stores it in a storage capacitor. The structure of the buck-boost converter is simplified by using one external inductor and applying time division technique using an arbiter. In addition, to improve the efficiency of the system, the controller circuits of the converter are designed so that current consumption is minimized. The proposed circuit is designed with $0.35{\mu}m$ CMOS process. Simulation results show that the designed circuit consumes up to 490nA of current when all three input channels are active, and the maximum power efficiency is 92%. The chip area of the designed circuit is $1310{\mu}m{\times}1100{\mu}m$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2261-2266
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• 2012

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance analysis of Fixed Priority, Round Robin, TDMA and Lottery bus arbitration policies due to the data traffic concentration and propose the methods of performance improvement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.50-56
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• 2009

SoC(System on a Chip) has several masters, slaves, arbiter and decoder in bus architecture. Master initiates the data transactions like CPU, DMA and DSP and slave responses the data transactions like SRAM SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, SoC performance can be changed definitely. Fixed priority, round-robin, TDM arbitration are used in general arbitration method, In this study, we compose TLM algorithm and analyze general arbitration methods through TLM simulation. Consequently, we propose the hybrid bus arbitration policy and verify the performance, compared with the other arbitration methods.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2004.11a
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• pp.299-302
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• 2004

본 논문은 OCP(Open Core Protocol)에 호환되는 파이프라인 구조를 가진 시스템 버스와 MPEG 시스템에 적합한 메모리 버스를 갖는 계층 구조를 가지는 새로운 동기 세그먼트 버스를 제안한다. 이 구조는 MPEG 시스템의 모바일 제품에 사용되는 영상 데이터 처리를 위한 메모리 인터페이스에 기반을 둔 버스 구조와 Multi-master와 Multi-slave를 사용하여 고성능의 다중 처리를 위한 양방향 다중 버스 구조(bi-direction multiple bus architecture)를 가진다. 효율적인 데이터 처리를 위하여 파이프라인 stage와 결합된 Master와 Slave의 주소번지가 latency를 결정하며, 시스템의 특성에 따라서 IP 코어를 배치하였다. 제안된 버스는 저 전력 구현을 위하여 세그먼트 버스 구조를 가지고, 멀티미디어 SoC 시스템의 성능 저하 없이 다중 작업이 가능한 구조를 갖는다. Wirability를 고려하여 양방향 구조를 채택하였고, Testablility를 위하여 단방향(uni-direction) 구조와 대체 가능하다. 또한, Local arbiter의 수정만으로 Master의 추가가 가능한 확장 구조를 가진다. Latency를 줄이기 위하여 직접 제어 방식과 단순한 구조의 Central arbiter로 구현되었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.2009-2014
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• 2012

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance comparison of TDMA and Lottery bus arbitration policy developed recently due to farious conditions and propose the methods of performance improvement.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.11
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• pp.2703-2708
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• 2014

The conventional bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in arbitrating the bus. The efficiency of bus usage can be determined by the selection of arbitration method. Fixed Priority, Round-Robin, TDMA and Lottery arbitration policies are studied in the conventional arbitration method where the bus transaction cycle, the wait cycle and the priority are primarily considered. In this paper, we propose the arbitration method that considers the wait cycle. Furthermore, we verify the bus transaction cycle and the wait cycle compared with the other arbitration methods through TLM(Transaction Level Model).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1879-1884
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• 2013

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance analysis of Fixed Priority, Round Robin, TDMA and Lottery bus arbitration policies due to the data traffic concentration and propose the methods of performance improvement.