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Score Arbitration Scheme For Decrease of Bus Latency And System Performance Improvement  

Lee, Kook-Pyo (Dept. of Electronics Engineering, Inha University)
Yoon, Yung-Sup (Dept. of Electronics Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.2, 2009 , pp. 38-44 More about this Journal
Abstract
Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method bus system performance can be charged definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this stuff, we proposed the score arbitration method and composed TLM algorithm. Also we analyze the performance compared with general arbitration methods through simulation. In the future, bus arbitration policy will be developed with the basis of the score arbitration method and improve the performance of bus system.
Keywords
bus system; arbiter; Score arbitration; Transaction Level Model;
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