| 1 |
A. Bystrov, D.J .Kinniment and A. Yakovlev, "Priority Arbiters", in Proc. IEEE 6th internation Symp. ASYNC, pp.128-137, April. 2000.
|
| 2 |
Y. Xu, L. Li, Ming-lun Gao, B.Zhand, Zhao-yu Jiand, Gao-ming Du, W. Zhang, "An Adaptive Dynamic Arbiter for Multi-Processor SoC", Solid-State and Integrated Circuit Technology International Conf., pp.1993-1996, 2006.
|
| 3 |
K. Lahiri, A. Raghunathan, and G. Lakshminarayana, "The LOTTERYBUS On-Chip Communication Architecture", IEEE Trans. VLSI Systems, vol.14, no.6, 2006.
|
| 4 |
http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=234&partnum=S3C2510A
|
| 5 |
이국표, 윤영섭, "마스터와 슬레이브에 따른 싱글버스와 다중버스 토폴로지의 성능분석", 전자공학회논문지, 제45권 SD편 제9호, pp. 96-102, 2008.
과학기술학회마을
|
| 6 |
R. Lu and C.-K. Koh, "SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips", IEEE Trans. on VLSI Systems, vol. 15, no. 1, pp.69-79, 2007.
DOI
ScienceOn
|
| 7 |
Sonics, Inc., Mountain View, CA, "Silicon micronetworks technical overview", 2002.
|
| 8 |
AMBA TM Specification(AHB) (Rev 2.0), ARM Ltd, May 1999.
|
| 9 |
J. G. Delgado-Frias and R. Diaz, "A VLSI selfcompacting buffer for DAMQ communication switches", in Proc. IEEE 8th Great Lakes Symp. VLSI, pp.128-133, Feb. 1998.
|
| 10 |
L. N. Bhuyan, "Analysis of interconnection networks with different arbiter designs", J.Parallel Distrib. Comput., vol.4, no.4, pp.384-403, 1987.
DOI
ScienceOn
|
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