Browse > Article
http://dx.doi.org/10.6109/jkiice.2013.17.8.1879

Performance Improvement of 2nd Arbitration in the Lottery Bus Arbitration Method  

Lee, Kookpyo (Department of Electro Info-Communication, Yeungjin College)
Koh, Si-Young (Department of Electronics, Kyungil University)
Abstract
The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance analysis of Fixed Priority, Round Robin, TDMA and Lottery bus arbitration policies due to the data traffic concentration and propose the methods of performance improvement.
Keywords
AMBA; SoC; bus architecture; arbitration;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 A. Bystrov, D.J .Kinniment and A. Yakovlev, "Priority Arbiters", in Proc. IEEE 6th internation Symp. ASYNC, pp.128-137, April. 2000.
2 K. Lee and S. Koh, "Characteristic comparison of various arbitration policies using TLM method", J.Korea Inst. Inf. Commun., Vol. 13 No. 8, pp.1653-1658, 2009.   과학기술학회마을
3 R. Lu and C.-K. Koh, "SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips", IEEE Trans. on VLSI Systems, vol. 15, no. 1, pp.69-79, 2007.   DOI   ScienceOn
4 Sonics, Inc., Mountain View, CA, "Silicon micronetworks technical overview", 2002.
5 AMBA TM Specification(AHB) (Rev 2.0), ARM Ltd, May 1999.
6 L. N. Bhuyan, "Analysis of interconnection networks with different arbiter designs", J.Parallel Distrib. Comput., vol.4, no.4, pp.384-403, 1987.   DOI   ScienceOn
7 http://www.samsung.com/global/business/semiconductor/ productInfo.do?fmly_id=234& partnum=S3C2510A
8 J. G. Delgado-Frias and R. Diaz, "A VLSI selfcompacting buffer for DAMQ communication switches", in Proc. IEEE 8th Great Lakes Symp. VLSI, pp.128-133, Feb. 1998.
9 Y. Xu, L. Li, Ming-lun Gao, B.Zhand, Zhao-yu Jiand, Gao-ming Du, W. Zhang, "An Adaptive Dynamic Arbiter for Multi-Processor SoC", Solid-State and Integrated Circuit Technology International Conf., pp.1993-1996, 2006.
10 K. Lahiri, A. Raghunathan, and G. Lakshminarayana, "The LOTTERYBUS On-Chip Communication Architecture", IEEE Trans. VLSI Systems, vol.14, no.6, 2006.