Browse > Article
http://dx.doi.org/10.6109/jkiice.2014.18.11.2703

Bus Arbitration Considering Waiting cycle  

Lee, Kook-Pyo (Department of Electro Info-Communication, Yeungjin College)
Joung, Yang-Hee (Department of Electrical&Semiconductor Engineering, Chonnam National University)
Kang, Seong-Jun (Department of Electrical&Semiconductor Engineering, Chonnam National University)
Abstract
The conventional bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in arbitrating the bus. The efficiency of bus usage can be determined by the selection of arbitration method. Fixed Priority, Round-Robin, TDMA and Lottery arbitration policies are studied in the conventional arbitration method where the bus transaction cycle, the wait cycle and the priority are primarily considered. In this paper, we propose the arbitration method that considers the wait cycle. Furthermore, we verify the bus transaction cycle and the wait cycle compared with the other arbitration methods through TLM(Transaction Level Model).
Keywords
Bus Arbitration; Bus; Wait cycle; Soc;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 L. Benini and G. D. Micheli, "Networks on chips: A new SoC paradigm", IEEE Comput., vol.35, pp.70-78, Jan. 2002.
2 Y. Xu, L. Li, Ming-lun Gao, B.Zhand, Zhao-yu Jiand, Gao-ming Du, W. Zhang, "An Adaptive Dynamic Arbiter for Multi-Processor SoC", Solid-State and Integrated Circuit Technology International Conf., pp.1993-1996, 2006.
3 A. Bystrov, D.J .Kinniment and A. Yakovlev, "Priority Arbiters", in Proc. IEEE 6th internation Symp. ASYNC, pp.128-137, April. 2000.
4 AMBA TM Specification(AHB) (Rev 2.0), ARM Ltd, May 1999.
5 K. Lahiri, A. Raghunathan, and G. Lakshminarayana, "The LOTTERYBUS On-Chip Communication Architecture", IEEE Trans. VLSI Systems, vol.14, no.6, 2006.
6 K. Lee and S. Koh, "Characteristic comparison of various arbitration policies using TLM method", J.Korea Inst. Inf. Commun., Vol. 13 No. 8, pp.1653-1658, 2009.   과학기술학회마을
7 M. Jun, K. Bang, H. Lee and E. Chung, "Latency-aware bus arbitration for real-time embedded systems," IEICE Trans. Inf.& Syst.,vol .E90-D,no.3,2007.
8 R. Lu and C.-K. Koh, "SAMBA-Bus: A High Performance Bus Architecture for System-on- Chips", IEEE Trans. on VLSI Systems, vol. 15, no. 1, pp.69-79, 2007.   DOI   ScienceOn
9 E. Salminen, V. Lahtinen, K. Kuusilinna, and T. Hamalainen, "Overview of bus-based system-on-chip interconnections", in Proc. IEEE Int. Symp. Circuits Syst., pp. II-372-II-375, 2002.