• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1C
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• pp.77-86
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• 2010

In this paper, we present a noncoherent IR-UWB (Impulse Radio-Ultra Wide Band) ranging system with an AFE (Analog Front End) composed of a simple integrator and an 1-bit ADC (Analog-to-Digital Converter), and define AFE characteristics affecting the ranging performance. This system is realistic and easy to implement, since the integrator simply accumulates signal energies and the simple 1-bit ADC is applied instead of the multi-bit ADCs for coherent IR-UWB systems. On the other hand, its ranging accuracy is largely affected channel environments such as noise, multipath fading and so on, since the noncoherent receiver simply squares and integrates the received signals. However, despite these practical importances, there are few conventional researches on the performance analysis according to AFE characteristics in IR-UWB ranging systems. To this end, we analyze in this paper ranging performance according to AFE characteristics for the noncoherent IR-UWB ranging system in various wireless channel environments, and through these results we also present system parameters to be considered in UWB hardware designs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.85-90
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• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.31-39
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• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.

• Proceedings of the IEEK Conference
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• summer
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• pp.77-81
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• 2004

In this paper, we propose a analog front-end (AFE) for noncoherent On-Off Keying (OOK) Ultra Wide Band (UWB) system based on power detection. The proposed AFE are designed using 0.18 micron CMOS technology and verified by simulation using SPICE. The proposed AFE consist of Sample-and-Hold block, Analog-to-Digital converter, synchronizer, delayed clock generator and impulse generator. The time resolution of 1ns is obtained with 100MHz system clocks and the synchronized 10-bit digital outputs are delivered to the baseband. The impulse generator produces 1ns width pulse using digital CMOS gates. The simulation results show the feasibility of the proposed UWB AFE systems.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.130-137
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• 2013

This paper presents analog front-end(AFE) circuits for bio-potential measurement. The proposed AFE is composed of IA(instrument amplifier), BPF(band-pass filter), VGA(variable gain amplifier) and SAR(successive approximation register) type ADC. The low gm(LGM) circuits with current division technique and Miller capacitance with high gain amplifier enable IA to implement on-chip AC-coupling without external passive components. Spilt capacitor array with capacitor division technique and asynchronous control make the 12-b ADC with low power consumption and small die area. The total current consumption of proposed AFE is 6.3uA at 1.8V.

• ETRI Journal
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• v.31 no.6
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• pp.717-724
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• 2009

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 ${\mu}m$ CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 $mm^2$ and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.20-23
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• 2010

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.49-55
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• 2013

A high-voltage highly-integrated analog front-end (AFE) IC for medical ultrasound imaging applications is implemented using standard 0.18-${\mu}m$ CMOS process. The proposed AFE IC is composed of a high-voltage (HV) pulser utilizing stacked transistors generating up to 15 Vp-p pulses at 2.6 MHz, a low-voltage low-noise transimpedance preamplifier, and a HV switch for isolation between the transmit and receive parts. The designed IC consumes less than $0.15mm^2$ of core area, making it feasible to be applied for multi-array medical ultrasound imaging systems, including portable handheld applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.210-216
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• 2004

In this paper, we propose a noncoherent On-Off Keying (OOK) Ultra Wide Band (UWB) system based on power detection with noise power calibration for low power applications. The proposed UWB system achieves good bit error rate performance which is favorably comparable to that of the system using the ideal adaptive threshold, while maintaining simple receiver structure, In addition, low power Analog Front-End (AFE) blocks for the proposed noncoherent UWB transceiver are proposed and verified using CMOS technology. Simulation results on the pulse generator, delay time generator and 1-bit Analog-to-Digital (AID) converter show feasibility of the proposed UWB AFE system.

• IT SoC Magazine
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• s.19
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• pp.37-42
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• 2007

이 글은 당사에서 개발 진행한 TDMB,ISDB-T등의 Moblie TV Receiver단의 Analog Front-End SIP들의 Test H/W, S/W제작 경험을 바탕으로 보다 효율적이고 성공적인 SIP 개발이 될 수 있도록 도움을 주고자 기술 하였다.