• Title/Summary/Keyword: adder

Search Result 315, Processing Time 0.025 seconds

Implementation of Arithmetic Processor Using Multi-Valued Logic (다치 논리를 이용한 연산기 구현)

  • 양대영;김휘진;박진우;송홍복
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 1998.05a
    • /
    • pp.338-341
    • /
    • 1998
  • This paper presents CMOS full adder design method based on carry-propagation-free addition trees and a circuit technique, so called multiple-valued current-nude(MVCM) circuits. The carry-propagation-free addition method uses a redundant digit sets called redundant positive-digit number representations. The carry-propagation-free addition is by three steps, and the adder can be designed directly and efficiently from the algorithm using WVCM circuit, Also Multiplier can be designed by these adder. We demonstrate the effectiveness of the proposed method through simulation(SPICE).

  • PDF

CMOS Clockless Wave Pipelined Adder Using Edge-Sensing Completion Detection (에지완료 검출을 이용한 클럭이 없는 CMOS 웨이브파이프라인 덧셈기 설계)

  • Ahn, Yong-Sung;Kang, Jin-Ku
    • Journal of IKEEE
    • /
    • v.8 no.2 s.15
    • /
    • pp.161-165
    • /
    • 2004
  • In this paper, an 8bit wave pipelined adder using the static CMOS plus Edge-Sensing Completion Detection Logic is presented. The clockless wave-pipelining algorithm was implemented in the circuit design. The Edge-Sensing Completion Detection (ESCD) in the algorithm is consisted of edge-sensing circuits and latches. Using the algorithm, skewed data at the output of 8bit adder could be aligned. Simulation results show that the adder operates at 1GHz in $0.35{\mu}m$ CMOS technology with 3.3V supply voltage.

  • PDF

Design of 32-bit Carry Lookahead Adder Using ENMODL (ENMODL을 이용한 32 비트 CLA 설계)

  • 김강철;이효상;송근호;서정훈;한석붕
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.3 no.4
    • /
    • pp.787-794
    • /
    • 1999
  • This paper presents an ENMODL(enhances NORA MODL) circuit and implements a high-speed 32 bit CLA(carry lookahead adder) with the new dynamic logics. The proposed logic can reduce the area and the Propagation delay of carry because output inverters and a clocking PMOS of second stage can be omitted in two-stage MODL(multiple output domino logic) circuits. The 32-bit CLA is implemented with 0.8um double metal CMOS Process and the carry propagation delay of the adder is about 3.9 nS. The ENMODL circuits can improve the performance in the high-speed computing circuits depending on the degree of recurrence.

  • PDF

Implementation of Ternary Adder and Multiplier Using Current-Mode CMOS (전류모드 CMOS에 의한 3치 가산기 및 승산기의 구현)

  • Seong, Hyeon-Kyeong
    • Proceedings of the KIEE Conference
    • /
    • 2006.10c
    • /
    • pp.142-144
    • /
    • 2006
  • In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under $1.5{\mu}m$ CMOS standard technology, $1.5{\mu}m$ unit current, and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.

  • PDF

Design of a Low-Power 8$\times$8 bit Parallel Multiplier Using Low-Swing CVSL Full Adder (Low-Swing CVSL 전가산기를 이용한 저 전력 8$\times$8 비트 병렬 곱셈기 설계)

  • Kang, Jang-Hee;Kim, Jeong-Beom
    • Proceedings of the KIEE Conference
    • /
    • 2005.05a
    • /
    • pp.144-147
    • /
    • 2005
  • This paper is proposed an 8$\times$8 bit parallel multiplier for low power consumption. The 8$\times$8 bit parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing tile previous works, this circuit is reduced the power consumption rate of 8.2% and the power-delay-product of 11.1%. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.35$\{\mu}m$ standard CMOS process.

  • PDF

Near-$V_{TH}$ Supply 64-Bit Adder using Bootstrapped CMOS Differential Logic (Bootstrapped CMOS Differential Logic 기술을 채용한 Near-$V_{TH}$ Supply에서 동작하는 64-Bit Adder 설계)

  • Oh, Jae-Hyuk;Jung, Byung-Hwa;Kong, Bai-Sun
    • Proceedings of the IEEK Conference
    • /
    • 2008.06a
    • /
    • pp.581-582
    • /
    • 2008
  • This paper describes novel bootstrapped CMOS differential logic family operating at near-Vth supply voltage. The proposed logic family provides improved switching speed by utilizing voltage bootstrapping for the supply voltage approaching device thresholds. The circuit is configured as differential structure having single bootstrapping capacitor, minimizing area overhead and providing complete logic composition capability. A 64-bit adder designed using the proposed technique in a 0.18um CMOS process provides up to 79% improvement in terms of power-delay product as compared to the conventional adder designed with DCVS.

  • PDF

Design of a Full-Adder Using Current-Mode Multiple-Valued Logic CMOS Circuits (전류 모드 CMOS 다치 논리 회로를 이용한 전가산기 설계)

  • Won, Young-Uk;Kim, Jong-Soo;Kim, Jeong-Beom
    • Proceedings of the KIEE Conference
    • /
    • 2003.11b
    • /
    • pp.275-278
    • /
    • 2003
  • This paper presents a full-adder using current-mode multiple valued logic CMOS circuits. This paper compares propagation delay, power consumption, and PDP(Power Delay Product) compared with conventional circuit. This circuit is designed with a samsung 0.35um n-well 2-poly 3-metal CMOS technology. Designed circuits are simulated and verified by HSPICE. Proposed full-adder has 2.25 ns of propagation delay and 0.21 mW of power consumption.

  • PDF

A Study on Constructing Highly Adder/multiplier Systems over Galois Felds

  • Park, Chun-Myoung
    • Proceedings of the IEEK Conference
    • /
    • 2000.07a
    • /
    • pp.318-321
    • /
    • 2000
  • This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fie2, degree of uk terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for perform above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesize ${\alpha}$$\^$k/ generation module and control signal CSt generation module with A-cell and M-cell. Then, we propose the future research and prospects.

  • PDF

On the design of 64bit CLSA adder using the optimized algorithm (최적 알고리즘을 이용한 64비트 CLSA 가산기 설계)

  • 이영훈;김상수
    • Journal of the Korea Society of Computer and Information
    • /
    • v.4 no.3
    • /
    • pp.47-52
    • /
    • 1999
  • The efficiency of an adder which plays an important role in micro-process and DSP greatly depends on the kinds of carry generation method. So in this paper. I used both CLA excellent in the speed and CSA best in the chip-size. The 64bit adder is designed with high speed which is two optimum combination. Therefore this paper suggested the way of CLSA improving both speed and chip-size. and proved the excellence of the designed circuit.

Optimal Design for Heterogeneous Adder Organization Using Integer Linear Programming (정수 선형 프로그래밍을 이용한 혼합 가산기 구조의 최적 설계)

  • Lee, Deok-Young;Lee, Jeong-Gun;Lee, Jeong-A;Rhee, Sang-Min
    • Journal of KIISE:Computer Systems and Theory
    • /
    • v.34 no.8
    • /
    • pp.327-336
    • /
    • 2007
  • Lots of effort toward design optimizations have been paid for a cost-effective system design in various ways from a transistor level to RTL designs. In this paper, we propose a bit level optimization of an adder design for expanding its design space. For the bit-level optimization, a heterogeneous adder organization utilizing a mixture of carry propagation schemes is proposed to design a delay-area efficient adder which were not available in an ordinary design space. Then, we develop an optimization method based on Integer Linear Programming to search the expanded design space of the heterogeneous adder. The novelty of the Proposed architecture and optimization method is introducing a bit level reconstruction/recombination of IPs which have same functionality but different speed and area characteristics for producing more find-grained delay-area optimization.