한국정보통신학회:학술대회논문집 (Proceedings of the Korean Institute of Information and Commucation Sciences Conference)
- 한국해양정보통신학회 1998년도 춘계종합학술대회
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- Pages.338-341
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- 1998
다치 논리를 이용한 연산기 구현
Implementation of Arithmetic Processor Using Multi-Valued Logic
초록
This paper presents CMOS full adder design method based on carry-propagation-free addition trees and a circuit technique, so called multiple-valued current-nude(MVCM) circuits. The carry-propagation-free addition method uses a redundant digit sets called redundant positive-digit number representations. The carry-propagation-free addition is by three steps, and the adder can be designed directly and efficiently from the algorithm using WVCM circuit, Also Multiplier can be designed by these adder. We demonstrate the effectiveness of the proposed method through simulation(SPICE).
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