• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• Bulletin of the Korean Chemical Society
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• 제35권3호
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• pp.731-736
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• 2014

An organic junction transistor with a vertical structure based on an active layer of poly(3-hexylthiophene) was fabricated by facile micro-contact printing combined with the Langmuir-Schaefer technique, without conventional e-beam or photo-lithography. Direct printing and subsequent annealing of Au-nanoparticles provided control over the thickness of the Au electrode and hence control of the electrical contact between the Au electrode and the active layer, ohmic or Schottky. The junction showed similar current-voltage characteristics to an NPN-type transistor. Current through the emitter was simply controllable by the base voltage and a high transconductance of ~0.2 mS was obtained. This novel fabrication method can be applied to amplifying or fast switching organic devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.206-209
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• 2002

With the progress of semiconductor processing technology, avalanohe photodiodes (APDs) based on InP/InGaAs are used for high-speed optical receiver modules. Planar-type APDs give higher reliability than mesa-type APDs. However, Planar-type APDs are struggled with a problem of intensed electric field at the junction curvature, which causes edge breakdown phenomena at the junction periphery. In this paper, we focused on studying the effects of junction curvature for APDs performances by different etching processes followed by single diffusion to from p-n junction. The performance of each process is characterized by observing electric field profiles and carrier generation rates. From the results, it can be understood to predict the optimum structure, which can minimize edge breakdown and improve the manufacturability.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.603-606
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• 2005

In this paper, the formation and thermal stability of Ni-silicide using Ni-Pd alloys is studied for ultra shallow S/D junction of nano-scale CMOSFETs. There are no different effects when Ni-Pd is used in single structure and TiN capping structure. But, in case of Cobalt interlayer structure, it was found that Pure Ni had lower sheet resistance than Ni-Pd, because of a thick silicide. Also, Ni-Pd has merits that surface of silicide and interface between silicide and silicon have a good morphology characteristics. As a result, Ni-Pd is an optimal candidate for shallow S/D junction when cobalt is used for thermal stability.

• 한국전자파학회논문지
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• 제16권7호
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• pp.732-739
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• 2005

본 논문에서는 E-평면 T형 분기 도파관을 갖는 Ka대역(20/30 GHz) 다이플렉서의 설계 및 구현에 관해 논하였다. 본 논문의 도파관 다이플렉서는 송신 필터 및 수신 필터를 E-평면 T형 분기 도파관으로 연결하여 E-평면으로 대칭이 되도록 하였다. T형 분기 도파관을 E-평면으로 선택한 이유는 제작시 생기는 절단면을 전류 밀도가 가장 낮은 지역에 두어 PIM(Passive Intermodulation) 레벨을 줄이기 위해서이다. 본 논문의 다이플렉서는 등가 모델을 사용하여 최적 설계를 수행함으로써 해석 시간을 줄이고자 하였다. 또한, 고전력 전송이 가능한 구조로 설계한 후 멀티팩션 해석을 수행하였으며, 해석 결과는 12 dB 마진을 확보하여 ESA/ESTEC 권고 사항을 만족함을 보였다. 제작된 다이플렉서는 전기적 성능 시험 결과를 통해 송수신 대역에서 반사 손실 22 dB 이상, 삽입 손실 0.20 dB 이하, 그리고 -40 dB 이하의 격리도 특성을 가져 요구 사항을 만족함을 보였고, 이로써 설계 결과가 검증되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.59-65
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• 2012

A study on the electrical characteristic analysis of solar cell diodes under experimental conditions of varying temperature and frequency has been conducted. From the current-voltage (I-V) measurements, at the room temperature, we obtained the ideality factor (n) for Space Charge Region (SCR) and Quasi-Neutral Region (QNR) of 3.02 and 1.76, respectively. Characteristics showed that the value of n (at SCR) decreases with rising temperature and n (at QNR) increases with the same conditions. These are due to not only the sharply increased SCR current flow but the activated carrier recombination in the bulk region caused by defects such as contamination, dangling bonds. In addition, from the I-V measurements implemented to confirm the junction uniformity of cells, the average current dispersion was 40.87% and 10.59% at the region of SCR and QNR, respectively. These phenomena were caused by the pyramidal textured junction structure formed to improve the light absorption on the device's front surface, and these affect to the total diode current flow. These defect and textured junction structure will be causes that solar cell diodes have non-ideal electrical characteristics compared with general p-n junction diodes. Also, through the capacitance-voltage (C-V) measurements under the frequency of 180 kHz, we confirmed that the value of built-in potential is 0.63 V.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.263-267
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• 2014

Super junction trench gate power MOSFETs have been receiving attention in terms of the trade-off between breakdown voltage and on-resistance. The vertical structure of super junction trench gate power MOSFETs allows the on-resistance to be reduced compared with conventional Trench Gate Power MOSFETs. The heat release of devices is also decreased with the reduction of on-resistance. In this paper, Lattice Temperature of two devices, Trench Gate Power MOSFET and Super junction trench gate power MOSFET, are compared in several temperature circumstance with the same Breakdown Voltage and Cell-pitch. The devices were designed by 100V Breakdown voltage and measured from 250K Lattice Temperature. We have tried to investigate how much temperature rise in the same condition. According as temperature gap between top of devices and bottom of devices, Super junction trench gate power MOSFET has a tendency to generate lower heat release than Trench Gate Power MOSFET. This means that Super junction trench gate power MOSFET is superior for wide-temperature range operation. When trench etching process is applied for making P-pillar region, trench angle factor is also important component. Depending on trench angle, characteristics of Super junction device are changed. In this paper, we focus temperature characteristic as changing trench angle factor. Consequently, Trench angle factor don't have a great effect on temperature change.

• 한국진공학회지
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• 제9권2호
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• pp.167-171
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• 2000

AlGaAs/GaAs HBT의 동작특성에 미치는 에미터 구조의 영향을 조사하였다. 에미터의 크기 변화에 의해 차단주파수와 최대공진주파수가 변화하였으며, 이는 에미터 구조에 따라 저항과 접합용량이 변하기 때문이다. 또한 에미터의 주변길이와 접합면적도 HBT의 고주파 특성에 영향을 미치는 것을 알 수 있다.

• 전자공학회논문지A
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• 제31A권7호
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• pp.95-101
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• 1994

A novel concept for the analysis of planar devices with a field limiting ring(FLR) is presented which allows analytic expressions in a normalized form for the potential distributions of FLR structure. Based on the method of image charges the main and ring junctions with identical cylindrical edges are kept to be two different equipotential surfaces. The potential relations between main and ring junction of the FLR structure are compared with 2-dimensional device simulation program. MEDICI. A good accordance is found. Comparisions with experimental data reported for the optimum ring spacing and the relative improvement of the breakdowm voltages in the FLR sturcture show the validity of the concept. The normalized expressions allow a universal application regardless to the junction depths and background doping levels.

• Architectural research
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• 제8권2호
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• pp.37-42
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• 2006

Starting from the quadratic optimal control algorithm, this study obtains the relation of the performance index for constrained systems and Gauss's principle. And minimizing a function of the variation in kinetic energy at constrained and unconstrained states with respect to the velocity variation, the dynamic equation is derived and it is shown that the result compares with the generalized inverse method proposed by Udwadia and Kalaba. It is investigated that the responses of a 10-story building are constrained by the installation of a two-bar structure as an application to utilize the derived equations. The structural responses are affected by various factors like the length of each bar, damping, stiffness of the bar structure, and the junction positions of two structures. Under an assumption that the bars have the same mass density, this study determines the junction positions to minimize the total dynamic responses of the structure.