• International Journal of Quality Innovation
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• 제8권3호
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• pp.81-112
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• 2007

In the competitive global market, firms have to keep profit from innovation activities. A firm makes profits by offering products or services at a lower cost than its competitors or by offering differentiated products at premium prices that more than compensate for the extra cost of differentiation. The IC Package and Testing technology industries were the first high technological industry to build in Taiwan. The Package and Testing industries in Taiwan adopted competitive innovation activities to become stronger. In our study, we want to know how innovation activities influence a firm operating in the IC Package and Testing industries. Our study used a questionnaire and Likert five-point scale to survey the innovation activities, customer and feedback in innovation performance in the IC Package and Testing industry. The wafer level chip size packing technology in our study indicates the innovation activities. Because we need to compare the difference between the wafer level chip size packing technology and wire bonding technology to recognize innovation and how the innovator and customer were influenced. Our conclusions are described below: (1) When the innovator adopts innovation activities that can be maintained using experiments and knowledge, using machine and decision variables more quickly will produce success; (2) Innovators should adopt innovation activities that focus on customers that use knowledge and experimentation, training time and cost. If an innovation forces customers to spend much time and cost to learn new technology or applications, the innovation will not be adopted; (3) Innovators that create innovation performance higher than his customers must also consider the impact upon their customers. We have to remind innovator to focus on why their customers have a different level of evolution in the same innovation activities.

• 마이크로전자및패키징학회지
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• 제12권3호
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• pp.197-205
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• 2005

RF MEMS 기술에서 패키지의 개발은 매우 중요하다. RF MEMS 패키지는 소형화, hermetic 특성, 높은 RF 성능 및 신뢰성을 갖도록 설계되어야 한다. 또한 가능한 저온의 패키징 공정이 가능해야 한다. 본 연구에서는 저온 공정을 이용한 RF MEMS 소자의 hermetic 웨이퍼 레벨 패키징을 제안하였다. Hermetic sealing을 위하여 약 $300{\times}C$의 Au-Sn 공정 접합 (eutectic bonding) 기술을 사용하였으며, Au-Sn의 조합으로 형성된 sealing부의 폭은 $70{\mu}m$이었다. 소자의 전기적 연결을 위하여 기판에 수직 via hole을 형성하고 전기도금 (electroplating) 방법을 이용하여 Cu로 채웠다. 완성된 RF MEMS 패키지의 최종 크기는 $1mm\times1mm\times700{\mu}m$이었다. 패키징 공정의 최적화 및 $O_2$ 플라즈마 애싱 공정을 통하여 접합 계면 및 via hole의 void들을 제거할 수 있었다. 또한 패키지의 전단 강도 및 hermeticity는 MIL-STD-883F의 규격을 만족하였으며 패키지 내부에서 오염 및 기타 유기 물질은 발생하지 않았다. 패키지의 삽입 손실은 2 GHz에서 0.075 dB로 매우 작았으며, 여러 종류의 신뢰성 시험 결과 패키지의 파손 및 성능의 감소는 발견되지 않았다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 추계학술대회 논문집
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• pp.479-480
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• 2012

• 한국표면공학회지
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• 제56권3호
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• pp.180-184
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• 2023

Scholars have proposed wafer-level bonding and three-dimensional (3D) stacked integrated circuit (IC) and have investigated Cu-Cu bonding to overcome the limitation of Moore's law. However, information about quantitative Cu-Cu direct-bonding conditions, such as temperature, pressure, and interfacial adhesion energy, is scant. This study determines the optimal temperature and pressure for Cu-Cu bonding by varying the bonding temperature to 100, 150, 200, 250, and 350 ℃ and pressure to 2,303 and 3,087 N/cm². Various conditions and methods for surface treatment were performed to prevent oxidation of the surface of the sample and remove organic compounds in Cu direct bonding as variables of temperature and pressure. EDX experiments were conducted to confirm chemical information on the bonding characteristics between the substrate and Cu to confirm the bonding mechanism between the substrate and Cu. In addition, after the combination with the change of temperature and pressure variables, UTM measurement was performed to investigate the bond force between the substrate and Cu, and it was confirmed that the bond force increased proportionally as the temperature and pressure increased.

• 마이크로전자및패키징학회지
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• 제23권3호
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• pp.1-6
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• 2016

IoT 적용을 위해서는 다종 소자를 높은 connectivity 밀도로 집적화시키는 전자패키징 기술이 매우 중요하다. FOWLP 기술은 입출력 밀도가 높고, 소자의 집적화가 우수하고, 디자인 유연성이 우수하여, 최근 개발이 집중되고 있는 기술이다. 웨이퍼나 패널 기반의 FOWLP 기술은 초미세 피치 RDL 공정 기술과 몰딩 기술 개발이 최적화 되어야 할 것이다. 3D stacking 기술 특히 웨이퍼 본딩 후 TSV를 제조하는 방법(via after bonding)은 가격을 낮추면서 connectivity를 높이는데 매우 효과적이라 하겠다. 하지만 저온 웨이퍼 본딩이나 TSV etch stop 공정과 같이 아직 해결해야할 단위 공정들이 있다. Substrate 기술은 두께를 줄이고 가격을 낮추는 공정 개발이 계속 주목되겠지만, 칩과 PCB와의 통합설계(co-design)가 더욱 중요하게 될 것이다.

• 한국생산제조학회지
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• 제22권3_1spc호
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• pp.504-508
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• 2013

This paper describes in detail the life prediction models and simulations of thermal fatigue under different mold compounds and chip sizes for wafer-level embedded SiP. Three-dimensional finite element models are built to simulate the viscoplastic behaviors for various mold compounds and chip sizes. In particular, the bonding parts between a mold and silicon nitride (Si3N4) are carefully modeled, and the strain distributions are studied. Three different chip sizes are used, and the effects of the mold compounds are observed. Through the numerical studies, it is found that type-C, which has a relatively lower Young's modulus and higher CTE, has a better fatigue life than the other mold compounds. In addition, the $4{\times}4$ chip has a shorter life than the $6{\times}6$ and $8{\times}8$ chips.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.501-502
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• 2006

In-plane type micro piezoelectric micro grippers with pneumatic lines for manipulation biological cells and micro parts were designed, fabricated, and characterized. Micro grippers were fabricated through the final micro-sanding process after wafer level bonding between the etched 4' Si wafer with pneumatic channels and 4' glass wafer. Displacements between two jaws of fabricated micro grippers were linearly increased with applying voltages to piezoelectric actuator. In the case of applying 80 V, the displacement between two jaws was $160{\mu}m$. Using fabricated micro grippers, manipulation tests for biological cell and micro parts with the sizes less than $100{\mu}m$ are in process.

• 한국정밀공학회지
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• 제22권11호
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• pp.165-172
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• 2005

In MEMS (Micro-Electro-Mechanical System), packaging induced stress or stress induced structure deformation becomes increasing concerns since it directly affects the performance of the device. In the decoupled vibratory MEMS gyroscope, the main factor that determines the yield rate is the frequency difference between the sensing and driving modes. The gyroscope, packaged using the anodic bonding at the wafer level and EMC (epoxy molding compound) molding, has a deformation of MEMS structure caused by thermal expansion mismatch. This effect results in large distribution in the frequency difference, and thereby a lower yield rate. To improve the yield rate we propose a packaged SiOG (Silicon On Glass) process technology. It uses a silicon wafer and two glass wafers to minimize the wafer warpage. Thus the warpage of the wafer is greatly reduced and the frequency difference is more uniformly distributed. In addition. in order to increase robustness of the structure against deformation caused by EMC molding, a 'crab-leg' type spring is replaced with a semi-folded spring. The results show that the frequency shift is greatly reduced after applying the semi-folded spring. Therefore we can achieve a more robust vibratory MEMS gyroscope with a higher yield rate.

• 반도체디스플레이기술학회지
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• 제1권1호
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• pp.15-19
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• 2002

A new vacuum packaging process in wafer level is developed for the surface micromachining devices using glass silicon anodic bonding technology. The inside pressure of the packaged device was measured indirectly by the quality factor of the mechanical resonator. The measured Q factor was about 5$\times10^4$ and the estimated inner pressure was about 1 mTorr. And it is also possible to change the inside pressure of the packaged devices from 2 Torr to 1 mTorr by varying the amount of the Ti gettering material. The long-term stability test is still on the way, but in initial characterization, the yield is about 80% and the vacuum degradation with time was not observed.

• 대한전자공학회논문지SD
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• 제45권2호
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• pp.13-20
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• 2008

본 논문에서는 CMOS 이미지 센서의 웨이퍼 레벨 어셈블리를 위한 스페이스 제작 방법을 설명하였다. 스페이스 제작을 위해서 SU-8, PDMS, Si-interposer를 이용하는 세 가지 방법을 제안하였다. SU-8 스페이스에서는 균일한 두께 특성을 위해서 웨이퍼 회전 장치를 고안했으며, PDMS 스페이스에서는 glass/PDMS/glass 구조의 정렬 접합을 위해서 새로운 접합 방법을 제안하였다. Si-interposer를 이용한 스페이스 제작에서는 DRF을 이용한 접합 조건을 확립하였다. 세 가지의 실험 결과 Si-interposer를 이용한 스페이스 제작 시 glass/스페이스/glass 구조의 접합력이 가장 뛰어났으며, 접합력의 크기는 32.3MPa의 전단응력을 나타내었다.