• Transactions on Electrical and Electronic Materials
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• v.15 no.2
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• pp.91-95
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• 2014

This paper presents the structure and process technology of simple and low-cost wafer-level packaging (WLP) for thin film radio frequency (RF) devices. Low-cost practical micromachining processes were proposed as an alternative to high-cost processes, such as silicon deep reactive ion etching (DRIE) or electro-plating, in order to reduce the fabrication cost. Gold (Au)/Tin (Sn) alloy was utilized as the solder material for bonding and hermetic sealing. The small size fabricated WLP of $1.04{\times}1.04{\times}0.4mm^3$ had an average shear strength of 10.425 $kg/mm^2$, and the leakage rate of all chips was lower than $1.2{\times}10^{-5}$ atm.cc/sec. These results met Military Standards 883F (MIL-STD-883F). As the newly proposed WLP structure is simple, and its process technology is inexpensive, the fabricated WLP is a good candidate for thin film type RF devices.

• Transactions of the Society of Information Storage Systems
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• v.2 no.3
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• pp.163-168
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• 2006

Small form factor optical pickup (SFFOP) corresponding to BD specifications is strongly proposed for the next-generation portable storage device. In order to generate SFFOP, small sized optical pickup has been fabricated. We have developed a small sited optical pickup that is called the integrated optical pickup (IOP). The fabrication method of this system is mainly dependant on the use of the wafer based micro fabrication technology, which has been used in MEMS process such as photolithography, reactive ion etching, wafer bonding, and packaging process. This approach has the merits for mass production and high assembling accuracy. In this study, to generate the small sized optical pickup for high recording capacity, IOP corresponding to BD specifications has been designed and developed, including three main parts, 1) design, fabrication and evaluation of objective lens unit, 2) design and fabrication of IOP and 3) evaluation process of FES and TES.

• Journal of the Korean Vacuum Society
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• v.13 no.1
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• pp.1-8
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• 2004

The SOI wafer fabrication technique has been developed by using ion-cut process, based on proton implantation and wafer bonding techniques. It has been shown by TRIM simulation that 65 keV proton implantation is required for the standard SOI wafer (200 nm SOI, 400 nm BOX) fabrication. In order to investigate the optimum proton dose and primary annealing condition for wafer splitting, the surface morphologic change has been observed such as blistering and flaking. As a result, effective dose is found to be in the 6∼$9\times10^{16}$ $H^{+}/\textrm{cm}^2$ range, and the annealing at $550^{\circ}C$ for 30 minutes is expected to be optimum for wafer splitting. The depth distribution of implanted hydrogen has been experimentally confirmed by ERD and SIMS measurements. The microstructure evolution in the damaged layer was also studied by X-TEM analysis.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1995.04a
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• pp.939-954
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• 1995

We propose a policy for controlling the release of raw wafers into the semiconductor wafer fabrication lines. The proposed policy exploits up-to-date factory floor information gathered by tracking systems used to calculate the time and amount of a new release to minimize mean flow times and mean tardiness while maintaining the maximum output rates of the system. Extensive computer experiments show that the proposed policy results in significant improvements for the same output rates compared to existing release rules.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.261-264
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• 2007

We developed a non self-aligned poly-silicon TFTs fabrication process at two different temperatures on spin-coated polyimide layer above Si-wafer. After TFTs fabrication, the polyimide layer was mechanically released from the Si-wafer and the devices characteristics were compared. In addition self-heating and hot-carrier induced instabilities were analysed.

• Proceedings of the Korea Society for Simulation Conference
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• 2003.11a
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• pp.147-151
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• 2003

Yield enhancement in semiconductor fabrication is important. Even though DRAM yield loss may be attributed to many problems, the existence of defects on the wafer is one of the main causes. When the defects on the wafer form patterns, it is usually an indication for the identification of equipment problems or process variations. In this paper describes the techniques to automatically classify a failure pattern using a fail bit map.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.55.4-55
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• 2002

In the semiconductor fabrication, particle contamination is wide-spread and one of major causes to yield loss. Extensive testing has revealed that even careful handling of wafers during processing may cause photo-resist materials to flake off wafer edges. So, to remove the photo-resist at the outer 5mm of wafers, UV(Ultraviolet) rays are exposed. WEE (Wafer Edge Exposure) process station is the system that exposes the wafer edge as prespecified by controlling the positioning mechanism and maintaining the light intensity level In this work, WEE process station has been designed so as to significantly lower the amount of particle contamination which occurs even during the most r...

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1101-1106
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• 2005

The purpose of this study was to develop a process management system to manage ingot fabrication and the quality of the ingot. The ingot is the first manufactured material of wafers. Operating data (trace parameters) were collected on-line but quality data (measurement parameters) were measured by sampling inspection. The quality parameters were applied to evaluate the quality. Thus, preprocessing was necessary to extract useful information from the quality data. First, statistical methods were employed for data generation, and then modeling was accomplished, using the generated data, to improve the performance of the models. The function of the models is to predict the quality corresponding to the control parameters. The dynamic polynomial neural network (DPNN) was used for data modeling that used the ingot fabrication data.

• Journal of Korean Institute of Industrial Engineers
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• v.36 no.1
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• pp.42-51
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• 2010

The semiconductor industry is highly capital and technology intensive. Technology advancement on circuit design and process improvement requires chip makers continuously to invest a new fabrication facility that costs more than 3 billion US dollars. Especially major semiconductor companies recently started to discuss 450mm fabrication substituting existing 300mm fabrication of which facilities were initiated to build in 1998. If the plan is consolidated, the yield of 450mm facility would be more than doubled compared to existing 300mm facility. In steps of this important investment, facility layout has been acknowledged as one of the most important factors to be competitive in the market. This research proposes a new concept of semiconductor facility layout using hexagonal floor plan and its compatible material flow pattern. The main objective of this proposal is to improve the productivity of the unified layout that has been popularly used to build existing facilities. In this research, practical characteristics of the semiconductor fabrication are taken into account to develop a new layout alternative based on the analysis of Chung and Tanchoco (2009). The performance of the proposed layout alternative is analyzed using computer simulation and the results show that the new layout alternative outperforms the existing layout alternative, unified layout. However, a few questions on space efficiency to the new alternative were raised in communication with industry practitioners. These questions are left for a future study.

• Safety and Health at Work
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• v.2 no.1
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• pp.39-51
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• 2011

Objectives: This study was designed to evaluate exposure levels of various chemicals used in wafer fabrication product lines in the semiconductor industry where work-related leukemia has occurred. Methods: The research focused on 9 representative wafer fabrication bays among a total of 25 bays in a semiconductor product line. We monitored the chemical substances categorized as human carcinogens with respect to leukemia as well as harmful chemicals used in the bays and substances with hematologic and reproductive toxicities to evaluate the overall health effect for semiconductor industry workers. With respect to monitoring, active and passive sampling techniques were introduced. Eight-hour long-term and 15-minute short-term sampling was conducted for the area as well as on personal samples. Results: The results of the measurements for each substance showed that benzene, toluene, xylene, n-butyl acetate, 2-methoxy-ethanol, 2-heptanone, ethylene glycol, sulfuric acid, and phosphoric acid were non-detectable (ND) in all samples. Arsine was either "ND" or it existed only in trace form in the bay air. The maximum exposure concentration of fluorides was approximately 0.17% of the Korea occupational exposure limits, with hydrofluoric acid at about 0.2%, hydrochloric acid 0.06%, nitric acid 0.05%, isopropyl alcohol 0.4%, and phosphine at about 2%. The maximum exposure concentration of propylene glycol monomethyl ether acetate (PGMEA) was 0.0870 ppm, representing only 0.1% or less than the American Industrial Hygiene Association recommended standard (100 ppm). Conclusion: Benzene, a known human carcinogen for leukemia, and arsine, a hematologic toxin, were not detected in wafer fabrication sites in this study. Among reproductive toxic substances, n-butyl acetate was not detected, but fluorides and PGMEA existed in small amounts in the air. This investigation was focused on the air-borne chemical concentrations only in regular working conditions. Unconditional exposures during spills and/or maintenance tasks and by-product chemicals were not included. Supplementary studies might be required.