Transactions on Electrical and Electronic Materials

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Design and Fabrication of a Low-cost Wafer-level Packaging for RF Devices

  • Lim, Jae-Hwan (Department of Information and Communication Engineering, Pukyong National University) ;
  • Ryu, Jee-Youl (Department of Information and Communication Engineering, Pukyong National University) ;
  • Choi, Hyun-Jin (MEMS/NANO Fabrication Center) ;
  • Choi, Woo-Chang (MEMS/NANO Fabrication Center)
  • Received : 2014.02.10
  • Accepted : 2014.02.27
  • Published : 2014.04.25
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Abstract

This paper presents the structure and process technology of simple and low-cost wafer-level packaging (WLP) for thin film radio frequency (RF) devices. Low-cost practical micromachining processes were proposed as an alternative to high-cost processes, such as silicon deep reactive ion etching (DRIE) or electro-plating, in order to reduce the fabrication cost. Gold (Au)/Tin (Sn) alloy was utilized as the solder material for bonding and hermetic sealing. The small size fabricated WLP of $1.04{\times}1.04{\times}0.4mm^3$ had an average shear strength of 10.425 $kg/mm^2$, and the leakage rate of all chips was lower than $1.2{\times}10^{-5}$ atm.cc/sec. These results met Military Standards 883F (MIL-STD-883F). As the newly proposed WLP structure is simple, and its process technology is inexpensive, the fabricated WLP is a good candidate for thin film type RF devices.

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References

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