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http://dx.doi.org/10.4313/TEEM.2014.15.2.91

Design and Fabrication of a Low-cost Wafer-level Packaging for RF Devices  

Lim, Jae-Hwan (Department of Information and Communication Engineering, Pukyong National University)
Ryu, Jee-Youl (Department of Information and Communication Engineering, Pukyong National University)
Choi, Hyun-Jin (MEMS/NANO Fabrication Center)
Choi, Woo-Chang (MEMS/NANO Fabrication Center)
Publication Information
Transactions on Electrical and Electronic Materials / v.15, no.2, 2014 , pp. 91-95 More about this Journal
Abstract
This paper presents the structure and process technology of simple and low-cost wafer-level packaging (WLP) for thin film radio frequency (RF) devices. Low-cost practical micromachining processes were proposed as an alternative to high-cost processes, such as silicon deep reactive ion etching (DRIE) or electro-plating, in order to reduce the fabrication cost. Gold (Au)/Tin (Sn) alloy was utilized as the solder material for bonding and hermetic sealing. The small size fabricated WLP of $1.04{\times}1.04{\times}0.4mm^3$ had an average shear strength of 10.425 $kg/mm^2$, and the leakage rate of all chips was lower than $1.2{\times}10^{-5}$ atm.cc/sec. These results met Military Standards 883F (MIL-STD-883F). As the newly proposed WLP structure is simple, and its process technology is inexpensive, the fabricated WLP is a good candidate for thin film type RF devices.
Keywords
Wafer-level packaging; Electrical through-connection; Highly productive process; Au-Sn bonding; Hermetic sealing;
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