• Proceedings of the KIEE Conference
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• 대한전기학회 1998년도 하계학술대회 논문집 B
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• pp.423-425
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• 1998

In this paper, a novel Programmable Signal Conditioner(PSC) for Thermo Couple(T/C) without variable-resistance is proposed. It is fabricated by using a fully digitalized error-correction and calibration algorithm. In signal processing of T/C, since the output voltage of T/C is nonlinear and its level is very low, the circuitry become very complicated to reduce the converting error and identify the true thermal voltage signal. The newly proposed PSC has compensation and calibration algorithm not using variable resistor. Moreover structure can be very simple and it has highly precise output characteristics.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제62권11호
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• pp.1604-1609
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• 2013

When the ground fault on the power side occurs on distribution system interconnected with distributed generations, the abnormal current is generated in the neutral conductor by the connection type and the iron core structure of transformers for the interconnection of distributed power supplies due to the unbalanced voltage of the system, and subsequently the false operation of the protective relay on the load side occurs. Herein, this paper proposes the method to correct errors in the phase current to prevent the false operation of the protective relay by applying p-q theory and presents the simulation result of the error correction algorithm using PSCAD/EMTDC.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제16권3호
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• pp.84-92
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• 2002

A size of low-voltage conductor cables is determined by the voltage drop of a system the cable impedance and the cable ampacity based on temperature correction factor in accordance with the condition of cable installation. Therefore, the proper temperation correction factor according to the condition of cable installation should be applied to determining the cable ampacity and also the skin effect and proximity effect, along with the kind and size of conductor and the condition of cable installation, should be properly considered to analyze the proper value of resistance and the reactance of the conductors. This paper addresses the systematic design flow for determining the size of low voltage level con여ctor cables in calculating the voltage drop of a power system and proposes a new improved the calculating formula what error should be minimized in comparison with the general formula and which can be applied in design work for determining the size of conductor cables.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.465-466
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• 2006

In this paper, novel analog duty cycle corrector (DCC) with a digital duty error detector is proposed. The digital duty error detector measures the duty error of the clock and converts it into a digital code. This digital code is then used to accurately correct the duty ratio by adaptively steering the charge-pump current. The proposed duty cycle corrector was implemented using an 80nm DRAM process with 1.8V supply voltage. The simulation result shows that the proposed duty cycle corrector improves the settling time up to $70{\sim}80%$ at 500MHz clock frequency for the same duty correction accuracy as the conventional analog DCC.

• Journal of information and communication convergence engineering
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• 제10권1호
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제48권10호
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• pp.25-32
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• 2011

We have analyzed adjacent cell dependency of threshold voltage shift caused by the cell to cell interference, and we proposed a 3-adjacent-cell model to model the pattern dependency of the threshold voltage shift. The proposed algorithm is verified by using MATLAB simulation and measurement results. In the experimental results, we found that accuracy of the proposed simple 3-adjacient-cell model is comparable to the widely used conventional 8-adjacient-cell model. The Bit Error Rate (BER) of LSB and of MSB is improved by 28.9% and 19.8%, respectively, by applying the proposed algorithm based on 3-adjacent-cell model to 20nm-class 2-bit MLC NAND flash memories.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제47권11호
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 한국조명전기설비학회 2005년도 춘계학술대회논문집
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• pp.106-110
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• 2005

In this paper, LED traffic signal lamp's operating circuit using Flyback converter and PFC IC has been presented. Most power conversion circuits use PFC IC for Power Factor Correction. The design parameter's value of Flyback converter has been proposed and the error amplifier which regulates the output voltage has been designed Besides, the under voltage protection circuit and the over voltage protection circuit for protecting the operating circuit kin unbalance of common electric power source and the temperature compensation circuit for fixed optical output power have been proposed.

• Journal of the Institute of Electronics and Information Engineers
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• 제52권12호
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• pp.109-117
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• 2015

In this paper, we proposed error-reducing method to source or measure a current or voltage for LED in the I-V characteristic analysis system using a digital signal processor (DSP). this method has the advantage of reducing a non-linear circuit error and random error. random error can be reduced using recursive averaging technique and non-linear circuit error can be reduced using 2rd polynomial regression calibration parameters fitting with measured sample data. it corrects measured error of IR, VR, VF1, VF2, VF3 of LED using calibration parameters. experimental results show that can be performed with about 0.017~0.043% accuracy.

• Journal of the Semiconductor & Display Technology
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• 제22권1호
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• pp.43-48
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• 2023

This paper discusses the design of 32Mbyte asynchronous nonvolatile memory modules, which includes self-diagnosis and RTC (Real Time Clock) functions to enhance their data stability and reliability. Nonvolatile memory modules can maintain data even in a power-off state, thereby improving the stability and reliability of a system or device. However, due to the possibility of data error due to electrical or physical reasons, additional data loss prevention methods are required. To minimize data error in asynchronous nonvolatile memory modules, this paper proposes the use of voltage monitoring circuits, self-diagnosis, BBT (Bad Block Table), ECC (Error Correction Code), CRC (Cyclic Redundancy Check)32, and data check sum, data recording method using RTC. Prototypes have been produced to confirm correct operation and suggest the possibility of commercialization.