Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Adaptive current-steering analog duty cycle corrector with digital duty error detection

디지털 감지기를 통해 전류 특성을 조절하는 아날로그 듀티 사이클 보정 회로

  • Choi, Hyun-Su (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, Chan-Kyung (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kong, Bai-Sun (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Jun, Young-Hyun (DRAM Design Team2, Memory Division, Samsung Electronics)
  • 최현수 (성균관대학교 정보통신공학부) ;
  • 김찬경 (성균관대학교 정보통신공학부) ;
  • 공배선 (성균관대학교 정보통신공학부) ;
  • 전영현 (삼성전자 메모리 사업부 DRAM 설계실)
  • Published : 2006.06.21
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Abstract

In this paper, novel analog duty cycle corrector (DCC) with a digital duty error detector is proposed. The digital duty error detector measures the duty error of the clock and converts it into a digital code. This digital code is then used to accurately correct the duty ratio by adaptively steering the charge-pump current. The proposed duty cycle corrector was implemented using an 80nm DRAM process with 1.8V supply voltage. The simulation result shows that the proposed duty cycle corrector improves the settling time up to $70{\sim}80%$ at 500MHz clock frequency for the same duty correction accuracy as the conventional analog DCC.

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