• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.57-66
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• 2014

This paper presents a low-complexity barrel distortion correction processor for wide-angle cameras. The proposed processor performs the barrel distortion correction jointly with the color demosaicking, so that the hardware complexity can be reduced significantly. In addition, to reduce the required memory bandwidth, an efficient memory interface is proposed by utilizing the spatial locality of the memory access in the correction process. The proposed processor is implemented with 35K logic gates in a $0.11-{\mu}m$ CMOS process and its correction speed is 150 Mpixels/s at the operating frequency of 606MHz, where the supported frame size is $2048{\times}2048$ and the required memory bandwidth is 1 read/cycle.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.50-59
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• 2000

Stereo vision is a technique extracting depth information from stereo images, which are two images that view an object or a scene from different locations. The most important procedure in stereo vision, which is called stereo matching, is to find the same points in stereo images. It is difficult to match stereo images in real time because stereo matching requires heavy calculation. In this Paper we design a digital VLSI to Process stereo matching in real time, which we call stereo image match processor (SIMP). For implementation of real time stereo matching, sliding memory and minimum selection tree are presented. SIMP is designed with pipeline architecture and parallel processing. SIMP takes 64 gray level 64$\times$64 stereo images and yields 8 level 64 $\times$64 disparity map by 3 bit disparity and 12 bit address outputs. SIMP can process stereo images with process speed of 240 frames/sec.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.281-286
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• 2002

In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.28-36
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• 2009

Sequence-Pair(SP) model represents the topological relation between modules. In general, SP model based floorplanners search solutions using Simulated-Annealing(SA) algorithm. Several SA based floorplanning techniques using SP model have been published. To improve the performance of those techniques they tried to improve the speed for evaluation function for SP model, to find better scheduling methods and perturb functions for SA. In this paper we propose a two phase SA based algorithm. In the first phase, white space between modules is reduced by applying compaction technique to the floorplan obtained by an SP. From the compacted floorplan, the corresponding SP is determined. Solution space has been searched by changing the SP in the SA framework. When solutions converge to some threshold value, the first phase of the SA based search stops. Then using the typical SA based algorithm, ie, without using the compaction technique, the second phase of our algorithm continues to find optimal solutions. Experimental results with MCNC benchmark circuits show that how the proposed technique affects to the procedure for SA based floorplainning algorithm and that the results obtained by our technique is better than those obtained by existing SA-based algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.10-17
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• 2011

As the data path of the processor widens and the depth of the pipeline deepens, the number of required registers increases. Consequently, careful attention must be paid to the design of clocked storage elements like latches and flipflops as they have a significant bearing on the overall performance of a synchronous VLSI circuit. As technology is also scaling down, noise immunity is becoming an important factor. In this paper, we present a new flipflop which has an improved noise immunity when compared to the hybrid latch flipflop and the conditional precharge flipflop. Simulation results in 65nm CMOS technology with 1.2V supply voltage are used to demonstrate the effectiveness of the proposed flipflop structure.

• Journal of IKEEE
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• v.12 no.1
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• pp.1-7
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• 2008

With the recent development of portable system such as mobile communication and multimedia. Full adders are important components in applications such as digital signal processors and microprocessors. Thus It is important to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional Ratioed logic and Pass Transistor logic. The proposed adder has the advantages over the conventional CMOS, TGA, 14T logic. The delay time is improved by 13% comparing to the average value and PDP(Power Delay Product) is improved by 9% comparing to the average value. Layouts have been carried out using a 0.18um CMOS design rule for evaluation purposes. The physical design has been evaluated using HSPICE.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.80-90
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• 1994

To develop VLSI of higher packing density with 0.5.mu.m gate length of less, semiconductor devices require shallow junction with higher doping concentration. the most common method to form the shallow junction is ion implantation, but in order to remove the implantation induced defect and activate the implanted impurities electrically, ion-implanted Si should be annealed at high temperature. In this annealing, impurities are diffused out and redistributed, creating deep PN junction. These make it more difficult to form the shallow junction. Accordingly, to miimize impurity redistribution, the thermal-budget should be kept minimum, that is. RTA needs to be used. This paper reports results of the diffusion characteristics of PSG film by varying Phosphorus weitht %/ Times and temperatures of RTA. From the SIMS.ASR.4-point probe analysis, it was found that low sheet resistance below 100 .OMEGA./ㅁand shallow junction depths below 0.2.mu.m can be obtained and the surface concentrations are measured by SIMS analysis was shown to range from 2.5*10$^{17}$ aroms/cm$^{3}$~3*10$^{20}$ aroms/cm$^{3}$. By depending on the RTA process of PSG film on Si, LDD-structured nMOSFET was fabricated. The junction depths andthe concentration of n-region were about 0.06.mu.m. 2.5*10$^{17}$ atom/cm$^{-3}$ , 4*10$^{17}$ atoms/cm$^{-3}$ and 8*10$^{17}$ atoms/cm$^{3}$, respectively. As for the electrical characteristics of nMOS with phosphorus junction for n- region formed by RTA, it was found that the characteristics of device were improved. It was shown that the results were mainly due to the reduction of electric field which decreases hot carriers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.81-90
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• 2004

For deep submicron (DSM) very large scale integrated circuits (VLSI), it is well known that interconnects have become the dominant factor in determining the overall circuit performance. Buffer insertion is an effective technique of interconnect optimization. When a net has an excessive propagation delay, one or more buffers can be inserted to reduce the delay. Buffers also reduce the crosstalk between neighboring wires. While many conventional methods insert buffers net by net. we have developed new techniques in which buffer locations are simultaneously optimized for all nets. This is to avoid the difficulties in finding the right ordering of nets for buffer insertion. since several nets may compete for a buffer location. We also study buffer insertion with multiple fan-out nets to optimize critical path delay. Elmore delay model is used for delay calculation and the number of buffers for each net is determined to optimize the delay.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1062-1070
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• 2002

In this paper, variable radix-two multibit coding algorithm is presented and applied in the implementation of discrete cosine transform(DCT) and inverse discrete cosine transform(IDCT). Variable radix-two multibit coding means the 2k SD (signed digit) representation of overlapped multibit scanning with variable shift method. SD represented by 2k generates partial products, which can be easily implemented with shifters and adders. This algorithm is most powerful for the hardware implementation of DCT/IDCT with constant coefficient matrix multiplication. This paper introduces the suggested algorithm, it's proof and the implementation of DCT/IDCT The implemented IDCT chip with 8 PEs(Processing Elements) and one transpose memory runs at a tate of 400 Mpixels/sec at 54MHz frequency for high speed parallel signal processing, and it's verified in HDTV and MPEG decoder.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.11
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• pp.979-983
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• 2013

The three-dimensional measurement method of confocal systems is a spot scanning method which has a high resolution and good illumination efficiency. However, conventional confocal systems had a weak point in that it has to perform XY axis scanning to achieve FOV (Field of View) vision through spot scanning. There are some methods to improve this problem involving the use of a galvano mirror [1], pin-hole array, etc. Therefore, in this paper we propose a method to improve a parallel mode confocal system using a micro-lens and pin-hole array in a dual microscope configuration. We made an area scan possible by using a combination MLA (Micro Lens Array) and pin-hole array, and used an objective lens to improve the light transmittance and signal-to-noise ratio. Additionally, we made it possible to change the objective lens so that it is possible to select a lens considering the reflection characteristic of the measuring object and proper magnification. We did an experiment using 5X, 2.3X objective lens, and did a calibration of height using a VLSI calibration target.