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Improved Simulated-Annealing Technique for Sequence-Pair based Floorplan  

Sung, Young-Tae (Department of Computer Engineering, Dong-A University)
Hur, Sung-Woo (Department of Computer Engineering, Dong-A University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.4, 2009 , pp. 28-36 More about this Journal
Abstract
Sequence-Pair(SP) model represents the topological relation between modules. In general, SP model based floorplanners search solutions using Simulated-Annealing(SA) algorithm. Several SA based floorplanning techniques using SP model have been published. To improve the performance of those techniques they tried to improve the speed for evaluation function for SP model, to find better scheduling methods and perturb functions for SA. In this paper we propose a two phase SA based algorithm. In the first phase, white space between modules is reduced by applying compaction technique to the floorplan obtained by an SP. From the compacted floorplan, the corresponding SP is determined. Solution space has been searched by changing the SP in the SA framework. When solutions converge to some threshold value, the first phase of the SA based search stops. Then using the typical SA based algorithm, ie, without using the compaction technique, the second phase of our algorithm continues to find optimal solutions. Experimental results with MCNC benchmark circuits show that how the proposed technique affects to the procedure for SA based floorplainning algorithm and that the results obtained by our technique is better than those obtained by existing SA-based algorithms.
Keywords
VLSI; Floorplan; Optimization; Sequence-pair; Simulated-annealing;
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