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Variable Radix-Two Multibit Coding and Its VLSI Implementation of DCT/IDCT  

김대원 (경북대학교 전자전기공학부)
최준림 (경북대학교 전자전기공학부)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.12, 2002 , pp. 1062-1070 More about this Journal
Abstract
In this paper, variable radix-two multibit coding algorithm is presented and applied in the implementation of discrete cosine transform(DCT) and inverse discrete cosine transform(IDCT). Variable radix-two multibit coding means the 2k SD (signed digit) representation of overlapped multibit scanning with variable shift method. SD represented by 2k generates partial products, which can be easily implemented with shifters and adders. This algorithm is most powerful for the hardware implementation of DCT/IDCT with constant coefficient matrix multiplication. This paper introduces the suggested algorithm, it's proof and the implementation of DCT/IDCT The implemented IDCT chip with 8 PEs(Processing Elements) and one transpose memory runs at a tate of 400 Mpixels/sec at 54MHz frequency for high speed parallel signal processing, and it's verified in HDTV and MPEG decoder.
Keywords
Booth's algorithm; DCT; IDCT; overlapped scanning; signed digit(SD) arithmetic; distributed arithmetic(DA); high speed multiplication;
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