Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Improvement of Delay and Noise Characteristics by Buffer Insertion

버퍼 삽입을 이용한 Delay와 Noise 특성 개선을 위한 연구

  • You, Man-Sung (Dept. of Electronics Engineering, Hanyang University) ;
  • Shin, Hyun-Chul (Dept. of Electronics Engineering, Hanyang University)
  • 유만성 (한양대학교 전자전기제어계측공학과) ;
  • 신현철 (한양대학교 전자컴퓨터공학부)
  • Published : 2004.06.30
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Abstract

For deep submicron (DSM) very large scale integrated circuits (VLSI), it is well known that interconnects have become the dominant factor in determining the overall circuit performance. Buffer insertion is an effective technique of interconnect optimization. When a net has an excessive propagation delay, one or more buffers can be inserted to reduce the delay. Buffers also reduce the crosstalk between neighboring wires. While many conventional methods insert buffers net by net. we have developed new techniques in which buffer locations are simultaneously optimized for all nets. This is to avoid the difficulties in finding the right ordering of nets for buffer insertion. since several nets may compete for a buffer location. We also study buffer insertion with multiple fan-out nets to optimize critical path delay. Elmore delay model is used for delay calculation and the number of buffers for each net is determined to optimize the delay.

집적회로 시스템이 고집적화 됨에 따라, 연결선은 회로 전체 성능을 결정하는 중요한 요소가 되었다. 버퍼 삽입은 연결선의 성능 향상의 효과적인 방법이다. 하나의 신호선이 허용 범위를 넘는 전달지연시간을 가질 때, 우리는 하나 또는 그 이상의 버퍼를 삽입하여 지연시간을 줄일 수 있다. 이제까지 많은 연구들에서 하나의 신호선에 대해 버퍼를 삽입하는 방법을 개발하였으나, 우리는 여러 신호선에 동시에 버퍼 위치를 찾아 버퍼를 삽입하는 방법을 연구하였다 이 방법은 여러 개의 신호선에 버퍼를 삽입하는 위치를 찾는 어려움을 효과적인 방법을 이용하여 그 위치를 결정한다. 또한 본 연구에서는 fan-out이 여럿인critical path에 대해서도 버퍼 삽입으로 지연시간을 최적화하는 기술을 개발하였다. 이 방법은 Elmore Delay 모델을 이용하여 지연시간을 계산하고 각 신호선에 지연시간을 최적화 할 수 있는 버퍼를 결정한다.

Keywords

References

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