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http://dx.doi.org/10.3745/KIPSTA.2002.9A.3.281

Implementation of a LSB-First Digit-Serial Multiplier for Finite Fields GF(2m)  

Kim, Chang-Hun (Dept.of Computer Information Engineering, Graduate School of Daegu University)
Hong, Chun-Pyo (Dept.of Information Communication Engineering, Daegu University)
U, Jong-Jeong (Dept.of Computer Information, Sungshin Women's University)
Abstract
In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.
Keywords
VLSI; Digit-Serial Architecture; Finite Field Multiplier; Cryptography; Systolic Array; Finite Field Arithmetic;
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