• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.647-650
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• 2005

In this paper, a low voltage SRAM using double boosting scheme is described. A low supply voltage deteriorates the static noise margin (SNM) and the cell read-out current. For read/write operation, a selected word line and cell VDD bias are boosted in a different level using double boosting scheme. This increases not only the static noise margin but also the cell readout current at a low supply voltage. A low voltage SRAM with 32K ${\times}$ 8bit implemented in a 0.18um CMOS technology shows an access time of 26.1ns at 0.8V supply voltage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.655-658
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• 1998

CMOS Reference Voltage Generator(RVG) is designed to possible CMOS process without additional process steps. It is possible to compensate the temperature of RVG by using PTAT(proportional to the absolute temperature). Temperature compensation is profitable because $\mun$ (electron mobility) is used. When VDD sweeps from 3V to 7V, variation ratio of Vref is 0.3125mV/V. Also temperature variation ratio of Vref is $047.1ppm/^{\circ}C$ during sweeping from $0^{\circ}C$ to $100^{\circ}C.$ Power Consumption is $50.3\muW.$

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.1650-1651
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• 2011

본 논문에서는 가변안내표지판(VMS)용 멀티-채널 LED Driver IC를 설계 연구 하였다. 설계한 LED Driver IC의 채널 수는 96 채널을 기본으로 하여 여분의 64채널을 추가로 구성하였다. VDD는 동작 환경에 따라 사용할 수 있게 12V, 6V, 3.3V로 구성하였다. 각 채널당 전류는 20mA로 일정한 전류가 흐를 수 있도록 하였다. 온도 변화에 따른 전류 변화로 인한 LED 휘도특성 변화를 줄이기 위해 트랜지스터를 여러단으로 쌓아 회로를 구성하였으며 내부 회로에 PTAT과 Bandgap Reference를 이용하여 트랜지스터에 안정적인 전원이 공급될 수 있게 구성하였다. 본 논문에 사용된 공정은 동부 0.13um 공정으로 최대 3.3V까지 사용할 수 있지만 12V및 6V에도 사용할 수 있게 트랜스지터를 쌓는 회로를 구성하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 B
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• pp.697-699
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• 1999

2기가비트급 이상의 Serial-Link Chip에 적용되는 PLL의 특성은 lock-in-time이 빨라야하며 low VDD 동작을 확보해야 한다. 본 논문은 2.8기가비트급의 인터페이스 전송칩에 사용되는 PLL에 내부 전원 공급기를 설계하여 외부전원 3.3V시에 2.5V를 제공하며 이를 PFD/CP/VCO에 개별적 적용하는 제어방법 및 회로를 제안하며 이에 따르는 IPLL의 Lock-In-Time을 1mS 이내로 설계하였으며 외부동작 주파수는 100MHz이상이며 인터페이스 전송량은 2.8기가비트에 이른다. 저전압 설계를 통한 동작전류를 내부 전원 제어를 통해 순차적(Sequential Method)동작을 시킴으로 IPLL 동작시의 전류소모을 2mA이하로 제한하였다. 본 논문에서는 2.8기가비트급 인터페이스 전송칩에 적용한 IPLL의 회로 및 내부전원 공급기의 제어 방법 및 설계결과를 제안하며 이에 따르는 전송칩의 동작방법을 제안한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.142-144
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• 2006

In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under $1.5{\mu}m$ CMOS standard technology, $1.5{\mu}m$ unit current, and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.547-548
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• 2008

Linearity improvement technique of transconductor is presented in the paper. In order to certify the linearity improvement of proposed transconductor, the 3rd-order Elliptic low-pass Gm-C filter which provides 5MHz cutoff is implemented by using the transconductor. According to the IIP3 measurement result of filters, proposed filter has higher IIP3 than normal source-degeneration filter; the In-band IIP3 of proposed and normal filter are 10.1 dBm and 7.5 dBm respectively. The filter is fabricated in 1P6M $0.18-{\mu}m$ CMOS while consuming the 3.3mW with 1.8 Vdd. The in-band input-referred noise voltage is $62.3{\mu}Vrms$ and the SFDR is 54.1 dB.

• 전기전자학회논문지
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• 제12권1호
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• pp.34-42
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• 2008

This paper proposes a new on-chip voltage down converter(VDC), which employs a new reference voltage generator(RVG). The converter adopts a temperature-independence reference voltage generator, and a voltage-up converter. The architecture of the proposed VDC has a high-precision, and it was verified based on a 0.25${\mu}m$ 1P5M standard CMOS technology. For 2.5V to 1.0V conversion, the RVG circuit has a good characteristics such as temperature dependency of only 0.2mV/$^{\circ}C$, and the voltage-up circuit has a good voltage deviation within ${\pm}$0.12% for ${\pm}$5% variation of supply voltage VDD. The output voltage is stabilized with ${\pm}$1mV for load current varying from 0 to 100mA.

• Journal of Chest Surgery
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• 제16권4호
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• pp.547-554
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• 1983

Implantation of Dual Chamber Pacemakers Which sense in the Atrium and the Ventricle, and sequentially or synchronously trigger impulses in the both chambers, has led us to the near realization of the ideal "Physiologic Pacing". We have experienced two cases of implantation of Dual chamber pacemaker in September and October, 1983. One patient was a 21-year-old male who had postoperative complete heart block since he was taken Total correction of TOF in May, 1983 . We implanted transvenously a dual chamber pacemaker, VDD type, through the left subclavian vein. In the other patient who came to the emergency room for partial obstruction of small bowels with severe abdominal pain, nausea and vomiting, in whom heart block was found, we implanted a DDD type pacemaker through the left subclavian puncture. The pacemakers have been functioning well postoperatively for more than two months, and the conditions of patient were uneventful.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.17-18
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• 2000

A low-power source driver for TFT-LCDs has been proposed using the triple charge sharing method that enhances the AC power saving efficiency of the prior charge sharing method. The AC power saving efficiency of the proposed source driver reaches 66.6%. In addition, a novel OP-AMP with low-quiescent current has been developed. The measured quiescent current of the OP-AMP is $5{\mu}A{\sim}7{\mu}A$ at VDD=5V and VSS=0V with load resistance of $2k{\Omega}$ and load capacitance of 300pF.

• 한국세라믹학회지
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• 제34권10호
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• pp.1060-1066
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• 1997

In this paper, the effects of La addition of PLZT thin film prepared by sol-gel method on the capacitor characteristics are investigated for gigabit generation DRAM applications. The addition of La on the PLZT capacitor results in a trade-off between charge storage density(Qc') and leakage current density(Jl). As La content increases, Qc' and permeability(εr) at 0V are reduced while Jl is significantly decreased. It is demonstrated that 5% La doping of PZT can substantially reduce Jl and also improve resistance to fatigue while incurring only minimal degradation of Qc'. Very low leakage current density (5×10-7 A/㎠ even at 125℃) and high charge storage density (100fC/㎛2) under VDD/2=1V conditions are achieved using 5% La doped PZT thin films for gigabit DRAM capacitor dielectrics. In addition, the fatigue and TDDB measurements indicate good reliability of the PLZT capacitors.