• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.47-55
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• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.26-34
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• 1998

This paper presents a characterization method for faults of circuit patterns on MCM(Multichip Module) or PCB(Printed Circuit Board) substrates with electron beams of a SEM(Scanning Electron Microscope) by inducing voltage contrast on the signal line. The experimentation employes dual potential electron beams for the fault characterization of circuit patterns with a commercial SEM without modifying its structure. The testing procedure utilizes only one electron gun for the generation of dual potential electron beams by two different accelerating voltages, one for charging electron beam which introduces the yield of secondary electron $\delta$ < 1 and the other for reading beam which introduces $\delta$ > 1. Reading beam can read open's/short's of a specific net among many test nets, simultaneously discharging during the reading process for the next step, by removing its voltage contrast. The experimental results of testing the copper signal lines on glass-epoxy substrates showed that the state of open's/short's had generated the brightness contrast due to the voltage contrast on the surface of copper conductor line, when the net had charged with charging electron beams of 7KV accelerating voltages and then read with scanning reading electron beams of 2KV accelerating voltages in 10 seconds. The experimental results with Au pads of a IC die and Au plated Cu pads of BGA substrates provided the simple test method of circuit lines with 7KV charging electron beam and 2KV reading beam. Thus the characterization method showed that we can test open and short circuits of the net nondestructively by using dual potential electron beams with one SEM gun.

• The Journal of Advanced Prosthodontics
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• v.9 no.3
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• pp.176-181
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• 2017

PURPOSE. The purpose of this study was to evaluate the marginal and internal gaps of Ni-Cr and Co-Cr copings, fabricated using the dental ${\mu}-SLA$ system. MATERIALS AND METHODS. Ten study dies were made using a two-step silicone impression with a dental stone (type IV) from the master die of a tooth. Ni-Cr (NC group) and Co-Cr (CC group) alloy copings were designed using a dental scanner, CAD software, resin coping, and casting process. In addition, 10 Ni-Cr alloy copings were manufactured using the lost-wax technique (LW group). The marginal and internal gaps in the 3 groups were measured using a digital microscope ($160{\times}$) with the silicone replica technique, and the obtained data were analyzed using the non-parametric Kruskal-Wallis H test. Post-hoc comparisons were performed using Bonferroni-corrected Mann-Whitney U tests (${\alpha}=.05$). RESULTS. The mean (${\pm}$ standard deviation) values of the marginal, chamfer, axial wall, and occlusal gaps in the 3 groups were as follows: $81.5{\pm}73.8$, $98.1{\pm}76.1$, $87.1{\pm}44.8$, and $146.8{\pm}78.7{\mu}m$ in the LW group; $76.8{\pm}48.0$, $141.7{\pm}57.1$, $80.7{\pm}47.5$, and $194.69{\pm}63.8{\mu}m$ in the NC group; and $124.2{\pm}52.0$, $199.5{\pm}71.0$, $67.1{\pm}37.6$, and $244.5{\pm}58.9{\mu}m$ in the CC group. CONCLUSION. The marginal gap in the LW and NC groups were clinically acceptable. Further improvement is needed for CC group to be used clinical practice.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.60-68
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• 2008

This work describes a re-configurable 10MS/s to 100MS/s, low-power 10b two-step pipeline ADC operating at a power supply from 0.5V to 1.2V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10b accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the MDAC while a switched-bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB. The ADC with an active die area of $0.98mm^2$ shows a maximum SNDR and SFDR of 56.0dB and 69.6dB, respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V and 60MS/s.

• Journal of Hospice and Palliative Care
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• v.18 no.3
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• pp.179-187
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• 2015

For patients who are near the end of life, an inevitable step is discussion of a do-not-resuscitate (DNR) order, which involves patients, their family members and physicians. To discuss DNR orders, patients and family members should know the meaning of the order and cardiopulmonary resuscitation (CPR) which includes chest compression, defibrillation, medication to restart the heart, artificial ventilation, and tube insertion in the respiratory tract. And the following issues should be considered as well: patients' and their families' autonomy, futility of treatment, and the right for death with dignity. Terminal cancer patients should be informed of what futility of treatment is, such as a low survival rate of CPR, unacceptable quality of life after CPR, and an irremediable disease status. In Korea, two different law suits related to life supporting treatments had been filed, which in turn raised public interest in death with dignity. Since the 1980s, knowledge of and attitude toward DNR among physicians and the public have been improved. However, most patients are still alienated from the decision making process, and the decision is often made less than a week before death. Thus, the DNR discussion process should be improved. Early palliative care should be adopted more widely.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• The Journal of Art Theory & Practice
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• no.13
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• pp.73-95
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• 2012

In terms of element and process, art today has already been fully systemized, yet tends to become even more systemized. All phases of creation and exhibition, appreciation and education, promotion and marketing are planned, adjusted, and decided within the order of a globalized, networked system. Each phase is executed, depending on the system of management and control and diverse means corresponding to the system. From the step of education, artists are guided to determine their styles and not be motivated by their desire to become star artists or running counter to mainstream tendency and fashion. In the process of planning an exhibition, the level of artist awareness is considered more significant than work quality. It is impossible to avoid such systems and institutions today. No one can escape or be freed from the influence of such system. This discussion addresses a serious distortion in the selection system as part of the system connotatively called "art museum system," especially to evaluate artistic achievement and aesthetic quality. Called "studio system" or "art star system," the system distinguishes successful minority from failed absolute majority and justifies the results, deciding discriminative compensations. The discussion begins from work by Hunter Jonakin and Dan Perjovschi. The key point of this discussion is not their art worlds but the shared truth referred by the two as the collusive "art market" and "art star system." Through works based on their experiences, the two artists refer to these systems which restrict and confine them. Jonakin's Jeff Koons Must Die! is avideo game conveying a critical comment on authoritative operation of the museum system and star system. In this work, participants, whether viewer or artist, are destined to lose: the game is unwinnable. Players take the role of a person locked in a museum where artist Jeff Koons' retrospective is held. The player can either look around and quietly observe the works, which causes a game-over, or he can blow the classical paintings to pieces and cause the artist Koons to come out and reprimand the player, also resulting in a game-over. Like Jonakin, Dan Perjovschi's some drawings also focuses on the status of the artist shrunken by the system. Most artists are ruined in a process of competition to survive within the museum system. As John Burger properly pointed out, out of the art systems today, public collections (art museums) and private collections have become "something unbearable." The system justifies the selection system of art stars and its frame of reference, disregarding the problem of producing numerable victims in its process. What should be underlined above all else is that the present selection system seriously shrinks art's creative function and its function of generating meaning. In this situation, art might fall to the level of entertainment, accessible to more people and compromising with popularity. This discussion is based on assumption and consciousness on the matter that this situation might cause catastrophic results for not only explicit victims of the system but also winners, or ones defined as winners. The system of art is probably possible only by desire or distortion stemmed from such desire. The system can be flourished only under the economic system of avarice: quantitatively expanding economy, abundant style, resort economy in Venice and Miami, and luxurious shopping malls with up-to-date facilities. The catastrophe here is ongoing, not a sudden emergence, and dynamic, leading the system itself to a devastating end.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.