• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.389-389
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• 2010

In this paper, an investigation of the benefits of gate oxide for 8" the manufacturing of Trench MOSFETs and its impact on device performance is presented. Layout dimensions of trench power MOSFETs have been continuously reduced in order to decrease the specific on-resistance, maintaining equal vertical dimensions. We discuss experimental results for devices with a pitch size down fabricated with an unconventional gate trench topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are observed the trench gate oxidation by SEM.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 C
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• pp.723-725
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• 1998

STI CMP process are substituting gradually for LOCOS(Local Oxidation of Silicon) process to be available below sub-0.5um technology and to get planarized. The other hand, STI CMP process(especially STI CMP with RIE etch back process) has some kinds of defect like Nitride residue, Torn Oxide defect, etc. In this paper, we studied how to reduce Torn Oxide defects after STI CMP with RIE etch back process. Although Torn Oxide defects which occur on Oxide on Trench area is not deep and not sever, Torn oxide defects on Moat area is sometimes very deep and makes the yield loss. We did test on pattern wafers witch go through Trench process, APCVD process, and RIE etch back process by using an REC 472 polisher, IC1000/SUV A4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the root causes of torn oxide defects.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.421-424
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• 2004

As the deep sub-micron devices are recently integrated high package density, novel process method for sub $0.1{\mu}m$ devices is required to get the superior thin gate oxide characteristics and reliability. However, few have reported on the electrical quality and reliability on the thin gate oxide. In this paper I will recommand a novel shallow trench isolation structure for thin gate oxide $30{\AA}$ of deep sub-micron devices. Different from using normal LOCOS technology, novel shallow trench isolation have a unique 'inverse narrow channel effects' when the channel width of the devices is scaled down shallow trench isolation has less encroachment into the active device area. Based on the research, I could confirm the successful fabrication of shallow trench isolation(STI) structure by the SEM, in addition to thermally stable silicide process was achiever. I also obtained the decrease threshold voltage value of the channel edge and the contact resistance of $13.2[\Omega/cont.]$ at $0.3{\times}0.3{\mu}m^2$. The reliability was measured from dielectric breakdown time, shallow trench isolation structure had tile stable value of $25[%]{\sim}90[%]$ more than 55[sec].

• Transactions on Electrical and Electronic Materials
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• 제17권5호
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• pp.302-305
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• 2016

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.

• 마이크로전자및패키징학회지
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• 제9권4호
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• pp.17-23
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• 2002

최근 반도체 소자의 고속화 및 고집적화에 따라 배선 패턴이 미세화 되고 다층의 금속 배선 공정이 요구됨에 따라 단차를 줄이고 표면을 광역 평탄화 시킬 수 있는 STI-CMP 공정이 도입되었다. 그러나, STI-CMP 공정이 다소 복잡해짐에 따라 질화막 잔존물, 찢겨진 산화막 결함들과 같은 여러 가지 공정상의 문제점들이 심각하게 증가하고 있다. 본 논문에서는 이상과 같은 CMP 공정 결함들을 줄이고, STI-CMP 공정의 최적 조건을 확보하기 위해 트렌치 깊이와 STI-fill 산화막 두께가 리버스 모트 식각 공정 후, 트랜치 위의 예리한 산화막의 취약함과 STI-CMP공정 후의 질화막 잔존물 등과 같은 결함들에 미치는 영향에 대해 연구하였다. 실험결과, CMP 공정에서 STI-fill의 두께가 얇을수록, 트랜치 깊이가 깊을수록 찢겨진 산화막의 발생이 증가하였다. 트랜치 깊이가 낮고 CMP 두께가 높으면 질화막 잔존물이 늘어나는 반면, 트랜치 깊이가 깊어 과도한 연마가 진행되면 활성영역의 실리콘 손상을 받음을 알 수 있었다

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.88-89
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• 2009

In this paper, we investigated about wet cleaning effect as deep trench formation methods for Power chip devices. Deep trench structure was classified by two methods, PSU (Poly Stick Up) and Non-PSU structure. In this paper, we could remove residue defect during wet. cleaning after deep trench etch process for non-PSU structure device as to change wet cleaning process condition. V-SEM result showed void image at the trench bottom site due to residue defect and residue component was oxide by EDS analysis. In order to find the reason of happening residue defect, we experimented about various process conditions. So, defect source was that oxide film was re-deposited at trench bottom by changed to hydrophobic property at substrate during hard mask removal process. Therefore, in order to removal residue defect, we added in-situ SCI during hard mask removal process, and defect was removed perfectly. And WLR (Wafer Level Reliability) test result was no difference between normal and optimized process condition.

• 한국정보통신학회논문지
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• 제14권6호
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• pp.1460-1464
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• 2010

본 논문에서는 MicroTec을 이용하여 Trench D-MOSFET의 항복전압을 분석하였다. 소자의 고집적을 위한 특성 분석 기술은 빠른 변화를 보이고 있다. 이에 따라 고집적 소자의 특성을 시뮬레이션을 통하여 이해하고 이에 맞게 제작하는 기술은 매우 중요한 과제 중의 하나가 되었다. Trench MOSFET은 고전압에서 가장 선호하는 전원장치이다. Trench MOSFET에서 산화막 두께와 도핑농도는 항복전압의 크기를 결정하며 고전압에 커다란 영향을 미치고 있다. 본 연구에서는 채널의 도핑 농도를 $10^{15}cm^{-3}$에서 $10^{17}cm^{-3}$까지 변화시켜 도핑 농도에 따른 항복전압 특성을 조사하였다. 또한 게이트 산화막 두께와 접합깊이를 변화시켜 항복전압 특성을 분석하였다.

• ETRI Journal
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• 제24권5호
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• pp.333-340
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• 2002

We propose a new process technique for fabricating very high-density trench MOSFETs using 3 mask layers with oxide spacers and a self-aligned technique. This technique reduces the device size in trench width, source, and p-body region with a resulting increase in cell density and current driving capability as well as cost-effective production capability. We were able to obtain a higher breakdown voltage with uniform oxide grown along the trench surface. The channel density of the trench DMOSFET with a cell pitch of 2.3-2.4 ${\mu}m$ was 100 Mcell/$in^2$ and a specific on-resistance of 0.41 $m{\Omega}{\cdot}cm^2$ was obtained under a blocking voltage of 43 V.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.183-184
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• 2005

In this paper. a new small size Lateral Trench Electrode Power IGBT is proposed. The entire electrode of proposed LIGBT is placed in trench oxide. The forward blocking voltage of the proposed LIGBT is improved by 1.6 times with that of the conventional LIGBT. The forward blocking voltage of proposed LIGBT is 500V. At the same size. a increase of the forward blocking voltage of about 1.6 times relative to the conventional LIGBT is observed by using TMA-MEDICI which is used for analyzing device characteristics. Because the electrodes of the proposed device are formed in trench oxide. the electric field in the device are crowded to trench oxide. We observed that the characteristics of i the proposed device was improved by using TMA-MEDICI and that the fabrication of the proposed device is possible by using TMA-TSUPREM4.

• 한국진공학회지
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• 제13권3호
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• pp.120-126
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• 2004

트렌치 소자 제조시 게이트 산화막 성장과 내압 강하의 원인이 되는 식각손상 회복과 코너 영역의 구조를 개선하기 위해 수소 분위기 열처리를 하였다. 열처리시 수소 원자에 의한 환원 반응을 이용하여 표면 에너지가 높은 코너 영역에서는 원자들의 이동에 의한 결정면 재배열, 산화막 측벽에서의 실리콘 원자 적층, 표면 거칠기의 개선 효과 등을 전자현미경 관찰을 통해 확인하였다. 실리콘 원자의 이동을 방해하는 식각 후 잔류 산화막을 수소 가스의 환원성 분위기에서 열처리함으로써 표면 에너지를 낮추는 방향으로 원자의 이동이 일어나 concave 영역, 즉 트렌치 bottom corner에서는 (111), (311) 결정면 재분포 현상이 일어남을 확인할 수 있었다. 또한 convex comer에서의 원자 이동으로 인해 corner 영역에서는 (1111) 면의 step 들이 존재하게 되고 원자 이동에 의해 산화막 측벽에 이르러 이동된 원자의 적층이 일어나며, 이는 열처리시 표면 손상 회복이 원자이동에 의함을 나타낸다. 이러한 적층은 표면 상태가 깨끗할수록 정합성을 띄어 기판과 일치하는 에피 특성을 나타내고 열처리 온도가 높을수록 표면 세정 효과가 커져 식각손상 회복효과가 커지며, 이를 이용하여 이후의 산화막 성장시 균일한 두께를 코너영역에서 얻을 수 있었다