• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.389-389
• /
• 2010

In this paper, an investigation of the benefits of gate oxide for 8" the manufacturing of Trench MOSFETs and its impact on device performance is presented. Layout dimensions of trench power MOSFETs have been continuously reduced in order to decrease the specific on-resistance, maintaining equal vertical dimensions. We discuss experimental results for devices with a pitch size down fabricated with an unconventional gate trench topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are observed the trench gate oxidation by SEM.

• Proceedings of the KIEE Conference
• /
• 1998.11c
• /
• pp.723-725
• /
• 1998

STI CMP process are substituting gradually for LOCOS(Local Oxidation of Silicon) process to be available below sub-0.5um technology and to get planarized. The other hand, STI CMP process(especially STI CMP with RIE etch back process) has some kinds of defect like Nitride residue, Torn Oxide defect, etc. In this paper, we studied how to reduce Torn Oxide defects after STI CMP with RIE etch back process. Although Torn Oxide defects which occur on Oxide on Trench area is not deep and not sever, Torn oxide defects on Moat area is sometimes very deep and makes the yield loss. We did test on pattern wafers witch go through Trench process, APCVD process, and RIE etch back process by using an REC 472 polisher, IC1000/SUV A4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the root causes of torn oxide defects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.421-424
• /
• 2004

As the deep sub-micron devices are recently integrated high package density, novel process method for sub $0.1{\mu}m$ devices is required to get the superior thin gate oxide characteristics and reliability. However, few have reported on the electrical quality and reliability on the thin gate oxide. In this paper I will recommand a novel shallow trench isolation structure for thin gate oxide $30{\AA}$ of deep sub-micron devices. Different from using normal LOCOS technology, novel shallow trench isolation have a unique 'inverse narrow channel effects' when the channel width of the devices is scaled down shallow trench isolation has less encroachment into the active device area. Based on the research, I could confirm the successful fabrication of shallow trench isolation(STI) structure by the SEM, in addition to thermally stable silicide process was achiever. I also obtained the decrease threshold voltage value of the channel edge and the contact resistance of $13.2[\Omega/cont.]$ at $0.3{\times}0.3{\mu}m^2$. The reliability was measured from dielectric breakdown time, shallow trench isolation structure had tile stable value of $25[%]{\sim}90[%]$ more than 55[sec].

• Transactions on Electrical and Electronic Materials
• /
• v.17 no.5
• /
• pp.302-305
• /
• 2016

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.

• Journal of the Microelectronics and Packaging Society
• /
• v.9 no.4
• /
• pp.17-23
• /
• 2002

The more productive and stable fabrication can be obtained by applying chemical mechanical polishing (CMP) process to shallow trench isolation (STI) structure in 0.18 $\mu\textrm{m}$ semiconductor device. However, STI-CMP process became more complex, and some kinds of defect such as nitride residue, tern oxide defect were seriously increased. Defects like nitride residue and silicon damage after STI-CMP process were discussed to accomplish its optimum process condition. In this paper, we studied how to reduce torn oxide defects and nitride residue after STI-CMP process. To understand its optimum process condition, We studied overall STI-related processes including trench depth, STI-fill thickness and post-CMP thickness. As an experimental result showed that as the STI-fill thickness becomes thinner, and trench depth gets deeper, more tern oxide were found in the CMP process. Also, we could conclude that low trench depth whereas high CMP thickness can cause nitride residue, and high trench depth and over-polishing can cause silicon damage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.88-89
• /
• 2009

In this paper, we investigated about wet cleaning effect as deep trench formation methods for Power chip devices. Deep trench structure was classified by two methods, PSU (Poly Stick Up) and Non-PSU structure. In this paper, we could remove residue defect during wet. cleaning after deep trench etch process for non-PSU structure device as to change wet cleaning process condition. V-SEM result showed void image at the trench bottom site due to residue defect and residue component was oxide by EDS analysis. In order to find the reason of happening residue defect, we experimented about various process conditions. So, defect source was that oxide film was re-deposited at trench bottom by changed to hydrophobic property at substrate during hard mask removal process. Therefore, in order to removal residue defect, we added in-situ SCI during hard mask removal process, and defect was removed perfectly. And WLR (Wafer Level Reliability) test result was no difference between normal and optimized process condition.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.6
• /
• pp.1460-1464
• /
• 2010

In the paper, the breakdown voltage of Trench D-MOSFET have been analyzed by using MircoTec. The technology for characteristic analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high-integrated device by computer simulation and fabricate the device having such characteristics became one of very important subjects. A Trench MOSFET is the most preferred power device for high voltage power applications. The oxide thickness and doping concentration in Trench MOSFET determines breakdown voltage and extensively influences on high voltage. We have investigated the breakdown voltage characteristics according to variation of doping concentration from $10^{15}cm^{-3}$ to $10^{17}cm^{-3}$ in this study. We have also investigated the breakdown voltage characteristics according to variation of oxide thickness and junction depth.

• ETRI Journal
• /
• v.24 no.5
• /
• pp.333-340
• /
• 2002

We propose a new process technique for fabricating very high-density trench MOSFETs using 3 mask layers with oxide spacers and a self-aligned technique. This technique reduces the device size in trench width, source, and p-body region with a resulting increase in cell density and current driving capability as well as cost-effective production capability. We were able to obtain a higher breakdown voltage with uniform oxide grown along the trench surface. The channel density of the trench DMOSFET with a cell pitch of 2.3-2.4 ${\mu}m$ was 100 Mcell/$in^2$ and a specific on-resistance of 0.41 $m{\Omega}{\cdot}cm^2$ was obtained under a blocking voltage of 43 V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.183-184
• /
• 2005

In this paper. a new small size Lateral Trench Electrode Power IGBT is proposed. The entire electrode of proposed LIGBT is placed in trench oxide. The forward blocking voltage of the proposed LIGBT is improved by 1.6 times with that of the conventional LIGBT. The forward blocking voltage of proposed LIGBT is 500V. At the same size. a increase of the forward blocking voltage of about 1.6 times relative to the conventional LIGBT is observed by using TMA-MEDICI which is used for analyzing device characteristics. Because the electrodes of the proposed device are formed in trench oxide. the electric field in the device are crowded to trench oxide. We observed that the characteristics of i the proposed device was improved by using TMA-MEDICI and that the fabrication of the proposed device is possible by using TMA-TSUPREM4.

• Journal of the Korean Vacuum Society
• /
• v.13 no.3
• /
• pp.120-126
• /
• 2004

A damage-reduced trench was investigated in view of the defect distribution along trench sidewall and bottom using high resolution transmission electron microscopy, which was formed by HBr plasma and additive gases in magnetically enhanced reactive ion etching system. Adding $O_2$ and other additive gases into HBr plasma makes it possible to eliminate sidewall undercut and lower surface roughness by forming the passivation layer of lateral etching. To reduce the RIE induced damage and obtain the fine shape trench corner rounding, we investigated the hydrogen annealing effect after trench formation. Silicon atomic migration on trench surfaces using high temperature hydrogen annealing was observed with atomic scale view. Migrated atoms on crystal surfaces formed specific crystal planes such as (111), (113) low index planes, instead of fully rounded comers to reduce the overall surface energy. We could observe the buildup of migrated atoms against the oxide mask, which originated from the surface migration of silicon atoms. Using this hydrogen annealing, more uniform thermal oxide could be grown on trench surfaces, suitable for the improvement of oxide breakdown.