• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.634-639
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• 2006

In this paper an MMIC 2-stage power amplifier is designed and fabricated for 5GHz wireless LAN applications using $0.5{\mu}m$ gate length PHEMT transistors. The PHEMT gate width is optimized in order to meet the linearity and efficiency of the MMIC power amplifier. The $0.5{\mu}m\times600{\mu}m$ PHEMT for the drive stage and $0.5{\mu}m\times3000{\mu}m$ PHEMT for the amplification stage are the optimized sizes to achieve more than 25dBc of third order IMD at the power level of 3dB back-off from the input P1dB and more than 22dBm output power under a supply voltage of 3.3V. The two-stage MMIC power amplifier is designed to be used for the both of HIPERLAN/2 and IEEE 802.11a because of its broadband characteristics. The fabricated PHEMT MMIC power amplifier exhibits a 20.1dB linear power gain, a maximum 22dBm output power, a 24% power added efficiency under 3.3V supply voltage. The input and output on-chip matching circuits are included on a chip of $1400\times1200{\mu}m^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.60-68
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• 2008

This work describes a re-configurable 10MS/s to 100MS/s, low-power 10b two-step pipeline ADC operating at a power supply from 0.5V to 1.2V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10b accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the MDAC while a switched-bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB. The ADC with an active die area of $0.98mm^2$ shows a maximum SNDR and SFDR of 56.0dB and 69.6dB, respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V and 60MS/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.71-80
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• 2007

This paper presents a new push-push VCO technique that extracts a second harmonic output signal from a capacitive commonnode in a negativegm oscillator topology. The generation of the $2^{nd}$ harmonics is accounted for by the nonlinear current-voltage characteristic of the emitter-base junction diode causing; 1) significant voltage clipping and 2) different rising and falling time during the switching operation of core transistors. Comparative investigations show the technique is more power efficient in the high-frequency region that a conventional push-push technique using an emitter common node. Prototype 12GHz and 17GHz MMIC VCO were realized in GaInP/GaAs HBT technology. They have shown nominal output power of -4.3dBm and -5dBm, phase noise of -108 dBc/Hz and -110.4 dBc/Hz at 1MHz offset, respectively. The phase noise results are also equivalent to a VCO figure-of-merit of -175.8 dBc/Hz and -184.3 dBc/Hz, while dissipate 25.68mW(10.7mA/2.4V) and 13.14mW(4.38mA/3.0V), respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Journal of IKEEE
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• v.17 no.1
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• pp.71-76
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• 2013

AlGaN/GaN HEMTs (High electron mobility transistors) with narrow channel were fabricated and the effect of channel scaling on the device were investigated. The devices were fabricated using e-beam lithography to have same channel length of $1{\mu}m$ and various channel width from 0.5 to $9{\mu}m$. The sheet resistance of the channel was increased corresponding to the decrease of channel width and the increase was larger at the width of sub-${\mu}m$. The threshold voltage of the HEMT with $1.6{\mu}m$ and $9{\mu}m$ channel width was -2.85 V. The transistor showed a variation of 50 mV at the width of $0.9{\mu}m$ and the variation 350 mV at $0.5{\mu}m$. The transconductance of 250 mS/mm was decreased to 150 mS/mm corresponding to the decrease of channel width. Also, the gate leakage current of the HEMT decreased with channel width. But the degree of was reduced at the width of sub-${\mu}m$. It was thought that the variation of the electrical characteristics of the HEMT corresponding to the channel width came from the reduced Piezoelectric field of the AlGaN/GaN structure by the strain relief.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.5
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• pp.55-65
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• 2000

In this paper a new architecture of 24-bit two's complement adder is designed by using RB(Redundant Binary) arithmetic which has the advantage of CPF(Carry-Propagation-Free). A MPPL(Modified PPL) XOR/XNOR gate is applied to improve a TC2RB(Two's Complement to RB SUM converter) speed and to reduce the number of transistors, and we proposed two types adder which used a fast RB2TC(RB SUM to Two's Complement converter). The property of two types adder is followings. The improvement of TYPE 1 adder speed is archived through the use of VGS(Variable Group Select) method and TYPE 2 adder is through the use of a 64-bit GCG(Group Change bit Generator) circuit and a 8-bit TYPE 1 adder. For 64-bit, TYPE 1 adder can be expected speed improvement of 23.5%, 25.7% comparing with the CLA and CSA, and TYPE 2 adder can be expected 41.2%, 45.9% respectively. The propagation delay of designed 24-bit TYPE 1 adder is 1.4ns and TYPE 2 adder is 1.2ns. The implementation is highly regular with repeated modules and is very well suited for microprocessor systems and fast DSP units.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.3
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• pp.214-218
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• 2020

In this study, Mg_xZn_1-xO thin films, which can be applied not only to active layers of light-emitting devices (LEDs), such as UV-LEDs, but also to solar cells, high mobility field-effect transistors, and power semiconductor devices, are fabricated using the sol-gel method. ZnO and Mg_0.3Zn_0.7O solution synthesized by the sol-gel method and the thin film were grown by spin coating on a Si (100) substrate and sapphire substrate. The solutions are synthesized by dissolving precursor materials in 2-methoxyethanol (2-ME) solvent, and then monoethanolamine (MEA) was added to the mixed solution as a sol stabilizer. Zinc acetate dihydrate is used as a ZnO precursor, while Mg nitrate hexahydrate and Mg acetate tetrahydrate are used as an MgO precursor. Then, the optical and structural characteristics of the fabricated thin films are compared. The molar concentration of the Zn precursor in the solvent is fixed at 0.3 M, and the amount of the Mg precursor is 30% of Mg²⁺/Zn²⁺. The optical characteristics are measured using an UV-vis spectrophotometer, and the transmittance of each wavelength is measured. Structural characteristics are measured using X-ray diffraction (XRD) and transmission electron microscopy (TEM). Composition analyses are performed using energy dispersive X-ray spectroscopy (EDS). The Mg_0.3Zn_0.7O thin film was well formed at the ratio of the Mg precursor added regardless of the type of Mg precursor, and the c-axis of the thin film was decreased, while the band gap was increased to 3.56 eV.

• Journal of the Korean Vacuum Society
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• v.12 no.4
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• pp.239-250
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• 2003

The reliability degradation phenomena in the SiGe hetero-junction bipolar transistor (HBT) are investigated in this review. In the case of the SiGe HBT the decrease of the current gain, the degradation of the AC characteristics, and the offset voltage are frequently observed, which are attributed to the emitter-base reverse bias voltage stress, the transient enhanced diffusion, and the deterioration of the base-collector junction due to the fluctuation in fabrication process, respectively. The reverse-bias stress on the emitter-base junction causes the recombination current to rise, increasing the base current and degrading the current gain, because hot carriers formed by the high electric field at the junction periphery generate charged traps at the silicon-oxide interface and within the oxide region. Because of the enhanced diffusion of the dopants in the intrinsic base induced by the extrinsic base implantation, the shorter distance between the emitter-base junction and the extrinsic base than a critical measure leads to the reduction of the cut-off frequency ($f_t$) of the device. If the energy of the extrinsic base implantation is insufficient, the turn-on voltage of the collector-base junction becomes low, in the result, the offset voltage appears on the current-voltage curve.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.7
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• pp.33-39
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• 2015

In this work, SU-8 passivated IZO thin-film transistors(TFTs) made by solution-processes was investigated for enhancing stability of indium zinc oxide(IZO) TFT. A very viscous negative photoresist SU-8, which has high mechanical and chemical stability, was deposited by spin coating and patterned on top of TFT by photo lithography. To investigate the enhanced electrical performances by using SU-8 passivation layer, the TFT devices were analyzed by X-ray phtoelectron spectroscopy(XPS) and Fourier transform infrared spectroscopy(FTIR). The TFTs with SU-8 passivation layer show good electrical characterestics, such as ${\mu}_{FE}=6.43cm^2/V{\cdot}s$, $V_{th}=7.1V$, $I_{on/off}=10^6$, SS=0.88V/dec, and especially 3.6V of ${\Delta}V_{th}$ under positive bias stress (PBS) for 3600s. On the other hand, without SU-8 passivation, ${\Delta}V_{th}$ was 7.7V. XPS and FTIR analyses results showed that SU-8 passivation layer prevents the oxygen desorption/adsorption processes significantly, and this feature makes the effectiveness of SU-8 passivation layer for PBS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1235-1242
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• 2008

In this paper, x-ray image sensor of photon counting type having a $32{\times}32$ pixel array is designed with $0.18{\mu}m$ triple-well CMOS process. Each pixel of the designed image sensor has an area of loot $100{\times}100\;{\mu}m2$ and is composed of about 400 transistors. It has an open pad of an area of $50{\times}50{\mu}m2$ of CSA(charge Sensitive Amplifier) with x-ray detector through a bump bonding. To reduce layout size, self-biased folded cascode CMOS OP amp is used instead of folded cascode OP amp with voltage bias circuit at each single-pixel CSA, and 15-bit LFSR(Linear Feedback Shift Register) counter clock generator is proposed to remove short pulse which occurs from the clock before and after it enters the counting mode. And it is designed that sensor data can be read out of the sensor column by column using a column address decoder to reduce the maximum current of the CMOS x-ray image sensor in the readout mode.