• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.481-482
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• 2022

In this paper, effect of random dopant fluctuation (RDF) of the top-transistor in a monolithic 3D inverter composed of MOSFET transistors is investigated with 3D TCAD simulation when the gate voltage of the bottom-transistor is changed. The sampling for investigating RDF effect was conducted through the kinetic monte carlo method, and the RDF effect on the threshold voltage variation in the top-transistor was investigated, and the electrical coupling between top-transistors and bottom-transistors was investigated.

• Journal of Sensor Science and Technology
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• v.32 no.6
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• pp.487-495
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• 2023

Over the past few decades, considerable research has been conducted on field-effect transistor (FET) biosensors; however, other than electrochemical sensors for pH, they have not reached the commercialization stage and still remain at the basic research level. Although several reports have been published on experiments with real biological samples, no reports exist of developments that have reached commercialization or finalized approval for use. In this paper, we explain the reason for the experiments of FET biosensors to induce spurious signals in an experimental setup and explain the existence of misunderstandings regarding the operating principle of FET biosensors owing to the spurious signals. Based on the thoughtful review of the results of previously published papers, we show that the electrochemical read-out principle of FET biosensors requires our intensive understanding of the interfacial potential between the solution and the sensor electrode for further progress in the FET biosensor research.

• Electronics and Telecommunications Trends
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• v.38 no.6
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• pp.52-61
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• 2023

With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

• Korean Chemical Engineering Research
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• v.60 no.2
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• pp.313-319
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• 2022

AlGaN/GaN based HfO₂ MOSHEMT (metal oxide semiconductor high electron transistor) with different gate recess depth was simulate to demonstrate a successful normally-off operation of the transistor. Three types of the HEMT structures including a conventional HEMT, a gate-recessed HEMT with 3 nm thick AlGaN layer, and MIS-HEMT without AlGaN layer in the gate region. The conventional HEMT showed a normally-on characteristics with a drain current of 0.35 A at V_G = 0 V and V_DS = 15 V. The recessed HEMT with 3 nm AlGaN layer exhibited a decreased drain current of 0.15 A under the same bias condition due to the decrease of electron concentration in 2DEG (2-dimensional electron gas) channel. For the last HEMT structure, distinctive normally- off behavior of the transistor was observed, and the turn-on voltage was shifted to 0 V.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.144-151
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• 2022

In this paper, a 1.5V 256kb eFlash memory IP with low area DC-DC converter is designed for battery application. Therefore, in this paper, 5V NMOS precharging transistor is used instead of cross-coupled 5V NMOS transistor, which is a circuit that precharges the voltage of the pumping node to VIN voltage in the unit charge pump circuit for the design of a low-area DC-DC converter. A 5V cross-coupled PMOS transistor is used as a transistor that transfers the boosted voltage to the VOUT node. In addition, the gate node of the 5V NMOS precharging transistor is made to swing between VIN voltage and VIN+VDD voltage using a boost-clock generator. Furthermore, to swing the clock signal, which is one node of the pumping capacitor, to full VDD during a small ring oscillation period in the multi-stage charge pump circuit, a local inverter is added to each unit charge pump circuit. And when exiting from erase mode and program mode and staying at stand-by state, HV NMOS transistor is used to precharge to VDD voltage instead of using a circuit that precharges the boosted voltage to VDD voltage. Since the proposed circuit is applied to the DC-DC converter circuit, the layout area of the 256kb eFLASH memory IP is reduced by about 6.5% compared to the case of using the conventional DC-DC converter circuit.

• Transactions on Electrical and Electronic Materials
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• v.16 no.2
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• pp.103-105
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• 2015

Effect of silicon doping into ZnSnO systems was investigated using solution process. Addition of silicon was used to suppress oxygen vacancy generation. The transfer characteristics of the device showed threshold voltage shift toward the positive direction with increasing Si content due to the high binding energy of silicon atoms with oxygen. As a result, the carrier concentration was decreased with increasing Si content.

• Journal of the Korean Society for Precision Engineering
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• v.25 no.8
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• pp.17-20
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• 2008

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.72-72
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• 2012

The next generation electronics need to not only be smaller but also be more flexible. To meet such demands, electronic devices using two dimensional (2D) atomic crystals have been studied intensely. Especially, graphene which have unprecedented performance fulfillments in versatile research fields leads a parade of 2D atomic crystals. In this talk, I will introduce the electrical characterization and applications of graphene for prominently electrical transistors realization. Even the rising 2D atomic crystals such as hexagonal boron nitride (h-BN), molybdenum disulfide (MoS2) and organic thin film for field effect transistor (FET) toward competent enhancement will be mentioned.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.44-47
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• 2000

본 연구는 α-Si:H TFT(Amorphous Silicon Thin Film Transistor)를 대체 할 펜타센을 활성층으로 사용하는 박막 트랜지스터를 제작에 관한 것이다. 유기 박막 트랜지스터는 유기발광소자와 함께 유연한 디스플레이에 응용된다. 펜타센 박막 트랜지스터의 제작은 채널 길이 25㎛, 70㎛, 소스, 드레인, 게이트 전극으로 Au을 lift off 공정으로 제작하였으며, 펜타센은 OMBD(Organic Molecular Beam Deposition)로 기판온도를 80℃로 유지하여 증착하였다. 제작된 소자로부터 트랜지스터 전류-전압 특성곡선을 측정하였고, 게이트에 의한 채널의 전도도가 조절됨을 확인하였다. 그리고, 전달특성곡선으로부터 문턱전압과 전계효과 이동도를 추출하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.171-172
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• 2018

Dual gate L-shaped tunnel field-effect-transistor (DG-LTFET) is presented in this study. DG-LTFET achieves near vertical subthreshold slope (SS) and its ON current is also found to be higher then both conventional TFET and LTFET. This device could serve as a potential replacement for conventional complimentary metal-oxide-semiconductor (CMOS) technology.