• 한국재료학회지
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• 제27권11호
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• pp.590-596
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• 2017

We demonstrated a CNT synaptic transistor by integrating 6,6-phenyl-C61 butyric acid methyl ester(PCBM) molecules as charge storage molecules in a polyimide(PI) dielectric layer with carbon nanotubes(CNTs) for the transistor channel. Specifically, we fabricated and compared three different kinds of CNT-based synaptic transistors: a control device with $Al_2O_3/PI$, a single PCBM device with $Al_2O_3/PI:PCBM$(0.1 wt%), and a double PCBM device with $Al_2O_3/PI:PCBM$(0.1 wt%)/PI:PCBM(0.05 wt%). Statistically, essential device parameters such as Off and On currents, On/Off ratio, device yield, and long-term retention stability for the three kinds of transistor devices were extracted and compared. Notably, the double PCBM device exhibited the most excellent memory transistor behavior. Pulse response properties with postsynaptic dynamic current were also evaluated. Among all of the testing devices, double PCBM device consumed such low power for stand-by and its peak current ratio was so large that the postsynaptic current was also reliably and repeatedly generated. Postsynaptic hole currents through the CNT channel can be generated by electrons trapped in the PCBM molecules and last for a relatively short time(~ hundreds of msec). Under one certain testing configuration, the electrons trapped in the PCBM can also be preserved in a nonvolatile manner for a long-term period. Its integrated platform with extremely low stand-by power should pave a promising road toward next-generation neuromorphic systems, which would emulate the brain power of 20 W.

• 한국정보전자통신기술학회논문지
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• 제9권1호
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• pp.120-131
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• 2016

본 논문에서는 back-gate bias 전압인 VNN (Negative Voltage)을 이용하여 5V의 MV (Medium Voltage) 소자만 이용하여 FN (Fowler-Nordheim) tunneling 방식으로 write하는 MTP cell을 사용하여 512비트 MTP IP를 설계하였다. 사용된 MTP cell은 CG(Control Gate) capacitor, TG(Tunnel Gate) transistor와 select transistor로 구성되어 있다. MTP cell size를 줄이기 위해 TG transistor와 select transistor를 위한 PW(P-Well)과 CG capacitor를 위한 PW 2개만 사용하였으며, DNW(Deep N-Well)은 512bit MTP cell array에 하나만 사용하였다. 512비트 MTP IP 설계에서는 BGR을 이용한 voltage regulator에 의해 regulation된 V1V (=1V)의 전압을 이용하여 VPP와 VNN level detector를 설계하므로 PVT variation에 둔감한 ${\pm}8V$의 pumping 전압을 공급할 수 있는 VPP와 VNN 발생회로를 제안하였다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1999년도 추계학술발표강연 및 논문개요집
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• pp.138-138
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• 1999

• Bulletin of the Korean Chemical Society
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• 제34권9호
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• pp.2563-2564
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• 2013

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2013년도 춘계학술대회 논문집
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• pp.173-174
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• 2013

• 한국재료학회:학술대회논문집
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• 한국재료학회 2005년도 춘계학술발표대회 및 제8회 신소재 심포지엄 논문개요집
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• pp.53-53
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• 2005

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2011년도 춘계학술대회 논문집
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• pp.579-580
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• 2011

• Bulletin of the Korean Chemical Society
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• 제33권5호
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• pp.1653-1658
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• 2012

A new anthracene-containing conjugated molecule was synthesized through the Sonogashira coupling and reduction reactions. 1-Ethynyl-4-hexylbenzene was coupled to 2,6-bis((4-hexylphenyl) ethynyl)anthracene-9,10-dione through a reduction reaction to generate 2,6,9,10-tetrakis((4-hexylphenyl)ethynyl) anthracene. The semiconducting properties were evaluated in an organic thin film transistor (OTFT) and a single-crystal field-effect transistor (SC-FET). The OTFT showed a mobility of around 0.13 $cm^2\;V^{-1}\;s^{-1}$ ($I_{ON}/I_{OFF}$ > $10^6$), whereas the SC-FET showed a mobility of 1.00-1.35 $cm^2\;V^{-1}\;s^{-1}$, which is much higher than that of the OTFT. Owing to the high photoluminescence quantum yield of 2,6,9,10-tetrakis((4-hexylphenyl)ethynyl) anthracene, we could observe a significant increase in drain current under irradiation with visible light (${\lambda}$ = 538 nm, 12.5 ${\mu}W/cm^2$).

• ETRI Journal
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• 제34권6호
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• pp.950-953
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• 2012

Schottky barrier single electron transistors (SB-SETs) and Schottky barrier single hole transistors (SB-SHTs) are fabricated on a 20-nm thin silicon-on-insulator substrate incorporating e-beam lithography and a conventional CMOS process technique. Erbium- and platinum-silicide are used as the source and drain material for the SB-SET and SB-SHT, respectively. The manufactured SB-SET and SB-SHT show typical transistor behavior at room temperature with a high drive current of $550{\mu}A/{\mu}m$ and $-376{\mu}A/{\mu}m$, respectively. At 7 K, these devices show SET and SHT characteristics. For the SB-SHT case, the oscillation period is 0.22 V, and the estimated quantum dot size is 16.8 nm. The transconductance is $0.05{\mu}S$ and $1.2{\mu}S$ for the SB-SET and SB-SHT, respectively. In the SB-SET and SB-SHT, a high transconductance can be easily achieved as the silicided electrode eliminates a parasitic resistance. Moreover, the SB-SET and SB-SHT can be operated as a conventional field-effect transistor (FET) and SET/SHT depending on the bias conditions, which is very promising for SET/FET hybrid applications. This work is the first report on the successful operations of SET/SHT in Schottky barrier devices.

• 한국전기전자재료학회논문지
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• 제31권5호
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• pp.273-277
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• 2018

This research introduces the sputtered IZO thin film transistor (TFT) with solution-processed $Al_2O_3$ diffusion layer. IZO is one of the most commonly used amorphous oxide semiconductor (AOS) TFT. However, most AOS TFTs have many defects that degrade performance. Especially oxygen vacancy in the active layer. In previous research, aluminum was used as a carrier suppressor by binding the oxygen vacancy and making a strong bond with oxygen atoms. In this paper, we use a solution-processed $Al_2O_3$ diffusion layer to fabricate stable IZO TFTs. A double-layer solution-processed $Al_2O_3$-sputtered IZO TFT showed better performance and stability, compared to normal sputtered IZO TFT.