• Journal of IKEEE
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• v.19 no.4
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• pp.500-505
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• 2015

Through Montecarlo simulation, this study compares how accurately the existing three phase deviation models estimate the time-varying variance of a planar oscillator perturbed by Gaussian noises. The comparison reveals that Kaertner model estimates the time-varying variance with about 1000 times higher accuracy than ISF or PP model exhibits. Additionally, it finds that the estimation accuracy of PP model is somewhat higher than that of ISF model.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.87-95
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• 2014

This paper describes a dual channel receiver design for CIS interfaces. Each channel includes CTLE(Continuous Time Linear Equalizer), sampler, deserializer and clocking circuit. The clocking circuit is composed of PLL, PI and CDR. Fast lock acquisition time, short latency and better jitter tolerance are achieved by adding OSPD(Over Sampling Phase Detector) and FSM(Finite State Machine) to PI-based CDR. The CTLE removes ISI caused by channel with -6 dB attenuation and the lock acquisition time of the CDR is below 1 baud period in frequency offset under 8000ppm. The voltage margin is 368 mV and the timing margin is 0.93 UI in eye diagram using 65 nm CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.43-53
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• 2007

We have analyzed low current operation characteristics of a VCSEL transmitter operating at fixed Current over wide temperature range. Used 850 nm oxide VCSEL has low temperature dependence of the threshold current and $d^2I_{th}/dT^2$ is approximately $1.346\times10^{-4}mA/^{\circ}C^2$. We fixed on-current so that output power from the chip is 1 mW at $20^{\circ}C$ and investigated the turn-on, turn-off characteristics and eye-diagram of the 850 nm oxide VCSEL transmitter with varying ambient temperature and off-current. We measured rise time, fall time, extinction ratio and timing jitter by changing tile ambient temperature and off-current. With the fixed off-current of around $0.1\sim0.2mA$ lower than the lowest threshold current the transmitter successfully operated at 1.25 Gbps over a wide temperature range from $-20^{\circ}C$ to $80^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.52-58
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• 2007

This paper describes the PLL of TCON(Timing Controller) chip for FPD(Flat Panel Display). The recent TCON requires wide range frequency operation of $8\sim135MHz$ in PLL. In order to be satisfied this requirement the new V-I converter.circuit. The V-I converter of new architecture increased the minimum/maximum current ratio which widens the operation frequency range of VCO's md also guaranteed linearity of VCO's. The proposed PLL circuits in FPD TCON show the measuring performance of loops RMS jitter in the range of $8\sim135MHz$. The designed circuit was fabricated in 1-ploy 3-metal 0.25um TSMC process technology and has a operation range or $8\sim135MHz$ with 2.5V power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.59-64
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• 2007

This paper describes the PLL of TCON(Timing Controller) chip for FPD(Flat Panel Display). We propose a new V-I converter which is insensitive to the power supply variation when it is applied to the TCON. The new V-I converter compensated the output frequency of VCO by appling the current that is inversely proportional to the voltage variation. The proposed idea is implemented with a 1-ploy 3-metal 0.25m TSMC CMOS technology and has the output frequency range from 192MHz to 360MHz at the supply voltage of 2.5V. Measurement result shows the RMS jitter of 100ps in the above output frequency range.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.1-12
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• 2020

Handling precise timing in high-speed transceivers has always been a primary design target to achieve better performance. Many different approaches have been tried, and one of those is utilizing the beneficial nature of injection locking. Though the phenomenon was not intended for building integrated circuits at first, its coupling effect between neighboring oscillators has been utilized deliberately. Consequently, the dynamics of the injection-locked oscillator (ILO) have been explored, starting from R. Adler. As many aspects of the ILO were revealed, further studies followed to utilize the technique in practice, suggesting alternatives to the conventional frequency syntheses, which tend to be complicated and expensive. In this review, the historical analysis techniques from R. Adler are studied for better comprehension with proper notation of the variables, resulting in numerical results. In addition, how the timing jitter or phase noise in the ILO is attenuated from noise sources is presented in contrast to the clock generators based on the phase-locked loop (PLL). Although the ILO is very promising with higher cost effectiveness and better noise immunity than other schemes, unless correctly controlled or tuned, the promises above might not be realized. In order to present the favorable conditions, several strategies have been explored in diverse applications like frequency multiplication, data recovery, frequency division, clock distribution, etc. This paper reviews those research results for clock multiplication and data recovery in detail with their advantages and disadvantages they are referring to. Through this review, the readers will hopefully grasp the overall insight of the ILO, as well as its practical issues, in order to incorporate it on silicon successfully.

• Korean Journal of Optics and Photonics
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• v.13 no.1
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• pp.58-64
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• 2002

Using Mach-Zehnder type intensity modulator, we stabilized a 10 GHz harmonically mode-locked dispersion-compensated fiber ring laser using a feedback controlling system, and we measured its stability. The laser was stabilized for more than 16 hours by controlling the cavity length to suppress the relaxation oscillation frequency component which had caused the laser output instability. The ms timing jitter and ms amplitude noise were measured to be 260-524 fsec and 4~11.5%, respectively, and BER test measurement showed a value of 10$^{-13}$ .

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.8
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• pp.861-866
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• 2014

This study evaluates the modeling accuracy of the existing three phase shift models on which the time domain oscillator phase noise theories are based. For the evaluation, this study investigates how accurately the three models can model the phase shift impulse train response of a simple planar oscillator. Evaluation result reveals that Kaertner model most accurately reflects the oscillator's phase shift impulse train responses for five different impulse train inputs, whereas PP model exhibited the worst performance in modeling the phase shift impulse train responses.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.6
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• pp.645-655
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• 1997

In this paper, the performance of the noncoherent code tracking loop designed at baseband for CDMA applications is analyzed in detail and is confirmed by computer simulations. Analytical closed-form formula for jitter variance is derived for AWGN channel environments as a function of pulse shaping filter, timing offset, signal-to-interference ratio, and loop filter coefficients. The design issue of the loop filter is also addressed with emphasis on the second-order tracking loop. Finally, the performance of the designed tracking loop is examined by computer simulations for both AWGN and Rayleigh fading channels, when applied to the reverse link of the coherent CDMA system for IMT-2000 designed by ETRI.

• ETRI Journal
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• v.29 no.5
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• pp.633-640
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• 2007

We report an experimental demonstration of 40 Gbps all-optical 3R regeneration with all-optical clock recovery based on InP semiconductor devices. We also obtain alloptical non-return-to-zero to return-to-zero (NRZ-to-RZ) format conversion using the recovered clock signal at 10 Gbps and 40 Gbps. It leads to a good performance using a Mach-Zehnder interferometric wavelength converter and a self-pulsating laser diode (LD). The self-pulsating LD serves a recovered clock, which has an rms timing jitter as low as sub-picosecond. In the case of 3R regeneration of RZ data, we achieve a 1.0 dB power penalty at $10^{-9}$ BER after demultiplexing 40 Gbps to 10 Gbps with an eletroabsorption modulator. The regenerated 3R data shows stable error-free operation with no BER floor for all channels. The combination of these functional devices provides all-optical 3R regeneration with NRZ-to-RZ conversion.