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http://dx.doi.org/10.5573/ieie.2014.51.10.087

A Receiver for Dual-Channel CIS Interfaces  

Shin, Hoon (College of Information and Communication Engineering, Sungkyunkwan University)
Kim, Sang-Hoon (College of Information and Communication Engineering, Sungkyunkwan University)
Kwon, Kee-Won (College of Information and Communication Engineering, Sungkyunkwan University)
Chun, Jung-Hoon (College of Information and Communication Engineering, Sungkyunkwan University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.10, 2014 , pp. 87-95 More about this Journal
Abstract
This paper describes a dual channel receiver design for CIS interfaces. Each channel includes CTLE(Continuous Time Linear Equalizer), sampler, deserializer and clocking circuit. The clocking circuit is composed of PLL, PI and CDR. Fast lock acquisition time, short latency and better jitter tolerance are achieved by adding OSPD(Over Sampling Phase Detector) and FSM(Finite State Machine) to PI-based CDR. The CTLE removes ISI caused by channel with -6 dB attenuation and the lock acquisition time of the CDR is below 1 baud period in frequency offset under 8000ppm. The voltage margin is 368 mV and the timing margin is 0.93 UI in eye diagram using 65 nm CMOS technology.
Keywords
CTLE; CDR; OSPD;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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