Browse > Article

A V-I Converter Design for Power Variation Insensitivity PLL  

Lee, Hyun-Seok (ADTechnology Co., LTD.)
Hong, Dong-Hee (Dept. of Computer Eng., Seokyeong Univ.)
Park, Jong-Wook (ADTechnology Co., LTD.)
Lim, Shin-Il (Dept. of Computer Eng., Seokyeong Univ.)
Sung, Man-Young (Dept. of Electrical Eng., Korea Univ.)
Publication Information
Abstract
This paper describes the PLL of TCON(Timing Controller) chip for FPD(Flat Panel Display). We propose a new V-I converter which is insensitive to the power supply variation when it is applied to the TCON. The new V-I converter compensated the output frequency of VCO by appling the current that is inversely proportional to the voltage variation. The proposed idea is implemented with a 1-ploy 3-metal 0.25m TSMC CMOS technology and has the output frequency range from 192MHz to 360MHz at the supply voltage of 2.5V. Measurement result shows the RMS jitter of 100ps in the above output frequency range.
Keywords
VCO; PLL; V-I Converter; LVDS; Synthesizer;
Citations & Related Records
연도 인용수 순위
  • Reference
1 J. G. Maneatis, 'Low-jitter and processindependent DLL and PLL based on self-biased techniques,' IEEE J. Solid-State Circuits, vol. 31, pp. 1728-1732, Nov. 1996
2 R. Jacob Baker, Harry W. Li, David E. Boyce 'CMOS Circuit Design, Layout and Simulation,' IEEE Press. Second Edition, pp.564-565, 2005
3 I. A. Young, J. K. Greason, and K. L. Wong ' A PLL Clock Generator with 5 to 110MHz of Lock Range for Microprocessors,' IEEE Journal of Solid-State Circuits, Vol. SC-27, pp. 1599-1607, November 1992. Presents the practical design of a CMOS delay element