Browse > Article

A V-I Converter Design for Wide Range PLL  

Hong, Dong-Hee (Dept. of Computer Eng., Seokyeong Univ.)
Lee, Hyun-Seok (ADTechnology Co., LTD.)
Park, Jong-Wook (ADTechnology Co., LTD.)
Sung, Man-Young (Dept. of Electrical Eng., Korea Univ.)
Lim, Shin-Il (Dept. of Computer Eng., Seokyeong Univ.)
Publication Information
Abstract
This paper describes the PLL of TCON(Timing Controller) chip for FPD(Flat Panel Display). The recent TCON requires wide range frequency operation of $8\sim135MHz$ in PLL. In order to be satisfied this requirement the new V-I converter.circuit. The V-I converter of new architecture increased the minimum/maximum current ratio which widens the operation frequency range of VCO's md also guaranteed linearity of VCO's. The proposed PLL circuits in FPD TCON show the measuring performance of loops RMS jitter in the range of $8\sim135MHz$. The designed circuit was fabricated in 1-ploy 3-metal 0.25um TSMC process technology and has a operation range or $8\sim135MHz$ with 2.5V power.
Keywords
VCO; Wide-Range; De-Skew; V-I Converter; PLL;
Citations & Related Records
연도 인용수 순위
  • Reference
1 I. A. Young, J. K. Greason, and K. L. Wong ' A PLL Clock Generator with 5 to 110MHz of Lock Range for Microprocessors,' IEEE Journal of Solid-State Circuits, Vol. SC-27, pp. 1599-1607, November 1992. Presents the practical design of a CMOS delay element
2 V. V. Kaenel et. al., 'A 320 MHz, 1.5 mW ${\circlea}$ 1.35V CMOS PLL for Microprocessor Clock Generation,' IEEE Journal of Solid-State Circuits, vol. 31, no. I pp. 1599-1607, NOV. 1992
3 R. Jacob Baker, Harry W. Li, David E. Boyce 'CMOS Circuit Design, Layout and Simulation,' IEEE Press. Second Edition, pp.564-565, 2005
4 J. G. Maneatis, 'Low-jitter and processindependent DLL and PLL based on self-biased techniques,' IEEE J. Solid-State Circuits, vol. 31, pp. 1728-1732, Nov. 1996