• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.179-184
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• 2016

In recent years, the on-resistance, power loss and cell density of Si power devices have not exhibited significant improvements, and performance is approaching the material limits. GaN is considered an attractive material for future high-power applications because of the wide band-gap, large breakdown field, high electron mobility, high switching speed and low on-resistance. Here we report on the Ohmic contact resistance and reverse-bias characteristics of AlGaN/GaN Schottky barrier diodes with and without annealing. Annealing in oxygen at $500^{\circ}C$ resulted in an increase in the breakdown voltage from 641 to 1,172 V for devices with an anode-cathode separation of $20{\mu}m$. However, these annealing conditions also resulted in an increase in the contact resistance of $0.183{\Omega}-mm$, which is attributed to oxidation of the metal contacts. Auger electron spectroscopy revealed diffusion of oxygen and Au into the AlGaN and GaN layers following annealing. The improved reverse-bias characteristics following annealing in oxygen are attributed to passivation of dangling bonds and plasma damage due to interactions between oxygen and GaN/AlGaN. Thermal annealing is therefore useful during the fabrication of high-voltage GaN devices, but the effects on the Ohmic contact resistance should be considered.

• Journal of the Microelectronics and Packaging Society
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• v.5 no.1
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• pp.7-18
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• 1998

In the flip chip interconnection on organic substrates using eutectic Pb/Sn solder bumps highly reliable Under Bump Metallurgy (UBM) is required to maintain adhesion and solder wettability. Various UBM systems such as 1$\mu$m Al/0.2$\mu$m Pd/1$\mu$m Cu, laid under eutectic Pb/Sn solder were investigated with regard to their interfacial reactions and adhesion proper-ties. The effects of numbers of solder reflow and aging time on the growth of intermetallic compounds (IMCs) and on the solder ball shear strength were investigated. Good ball shear strength was obtained with 1$\mu$m Al/0.2$\mu$m Ti/5$\mu$m Cu and 1$\mu$m Al/0.2$\mu$m ni/1$\mu$m Cu even after 4 solder reflows or 7 day aging at 15$0^{\circ}C$. In contrast 1$\mu$m Al/0.2$\mu$m Ti/1$\mu$m Cu and 1$\mu$mAl/0.2$\mu$m Pd/1$\mu$m 쳐 show poor ball shear strength. The decrease of the shear strength was mainly due to the direct contact between solder and nonwettable metal such as Ti and Al resulting in a delamination. In this case thin 1$\mu$m Cu and 0.2$\mu$m Pd diffusion barrier layer were completely consumed by Cu-Sn and pd-Sn reaction.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.202-208
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• 2001

In Recent results suggested that doping $Ta_2O_5$ with a small amount of $TiO_2$ using standard ceramic processing techniques can increase the dielectric constant of $Ta_2O_5$ significantly. In this paper, this concept is studied using RTCVD (Rapid Thermal Chemical Vapor Deposition). Ti-doped $Ta_2O_5$ films are deposited using $TaC_{12}H_{30}O_5N$, $C_8H_{24}N_4Ti$, and $O_2$ on both Si and $NH_3$-nitrided Si substrates. An $NH_3$-based interface layer at the Si surface is used to prevent interfacial oxidation during the CVD process and post deposition annealing is performed in $H_2/O_2$ ambient to improve film quality and reduce leakage current. A sputtered TiN layer is used as a diffusion barrier between the Al gate electrode and the $TaTi_xO_y$ dielectric. XPS analyses confirm the formation of a ($Ta_2O_5)_{1-x}(TiO_2)_x$ composite oxide. A high quality $TaTi_xO_y$ gate stack with EOT (Equivalent Oxide Thickness) of $7{\AA}$ and leakage current $Jg=O.5A/textrm{cm}^2$ @ Vg=-1.0V has been achieved. We have also succeeded in forming a $TaTi_x/O_y$ composite oxide by rapid thermal oxidation of the as-deposited CVD TaTi films. The electrical properties and Jg-EOT characteristics of these composite oxides are remarkably similar to that of RTCVD $Ta_2O_5, suggesting that the dielectric constant of $Ta_2O_5$ is not affected by the addition of $TiO_2$.

• Korean Journal of Materials Research
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• v.19 no.1
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• pp.28-32
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• 2009

Silicon carbide (SiC) is a promising material for power device applications due to its wide band gap (3.26 eV for 4H-SiC), high critical electric field and excellent thermal conductivity. The Schottky barrier diode is the representative high-power device that is currently available commercially. A field plate edge-terminated 4H-SiC was fabricated using a lift-off process for opening the Schottky contacts. In this case, Ni/Ti dual-metal contacts were unintentionally formed at the edge of the Schottky contacts and resulted in the degradation of the electrical properties of the diodes. The breakdown voltage and Schottky barrier height (SBH, ${\Phi}_B$) was 107 V and 0.67 eV, respectively. To form homogeneous single-metal Ni/4H-SiC Schottky contacts, a deposition and etching method was employed, and the electrical properties of the diodes were improved. The modified SBDs showed enhanced electrical properties, as witnessed by a breakdown voltage of 635 V, a Schottky barrier height of ${\Phi}_B$=1.48 eV, an ideality factor of n=1.04 (close to one), a forward voltage drop of $V_F$=1.6 V, a specific on resistance of $R_{on}=2.1m{\Omega}-cm^2$ and a power loss of $P_L=79.6Wcm^{-2}$.

• Journal of Sensor Science and Technology
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• v.14 no.2
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• pp.96-100
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• 2005

The planar Schottky diodes were fabricated and modeled to probe the device applicability of the cracked GaN epitaxial layer on a (111) silicon substrate. On the unintentionally n-doped GaN grown on silicon, we deposited Ti/Al/Ni/Au as the ohmic metal and Pt as the Schottky metal. The ohmic contact achieved a minimum contact resistivity of $5.51{\times}10.5{\Omega}{\cdot}cm^{2}$ after annealing in an $N_{2}$ ambient at $700^{\circ}C$ for 30 sec. The fabricated Schottky diode exhibited the barrier height of 0.7 eV and the ideality factor was 2.4, which are significantly lower than those parameters of crack free one. But in photoresponse measurement, the diode showed the peak responsivity of 0.097 A/W at 300 nm, the cutoff at 360 nm, and UV/visible rejection ratio of about $10^{2}$. The SPICE(Simulation Program with Integrated Circuit Emphasis) simulation with a proposed model, which was composed with one Pt/GaN diode and three parasitic diodes, showed good agreement with the experiment.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.387-387
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• 2013

Currently, the flash memory and the dynamic random access memory (DRAM) have been used in a variety of applications. However, the downsizing of devices and the increasing density of recording medias are now in progress. So there are many demands for development of new semiconductor memory for next generation. Magnetic random access memory (MRAM) is one of the prospective semiconductor memories with excellent features including non-volatility, fast access time, unlimited read/write endurance, low operating voltage, and high storage density. MRAM is composed of magnetic tunnel junction (MTJ) stack and complementary metal-oxide semiconductor (CMOS). The MTJ stack consists of various magnetic materials, metals, and a tunneling barrier layer. Recently, MgO thin films have attracted a great attention as the prominent candidates for a tunneling barrier layer in the MTJ stack instead of the conventional Al2O3 films, because it has low Gibbs energy, low dielectric constant and high tunneling magnetoresistance value. For the successful etching of high density MRAM, the etching characteristics of MgO thin films as a tunneling barrier layer should be developed. In this study, the etch characteristics of MgO thin films have been investigated in various gas mixes using an inductively coupled plasma reactive ion etching (ICPRIE). The Cl2/Ar, CH3OH/Ar, and CH4/Ar gas mix were employed to find an optimized etching gas for MgO thin film etching. TiN thin films were employed as a hard mask to increase the etch selectivity. The etch rates were obtained using surface profilometer and etch profiles were observed by using the field emission scanning electron microscopy (FESEM).

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.290.2-290.2
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• 2016

Recently, organic thin-film transistors have been widely researched for organic light-emitting diode panels, memory devices, logic circuits for flexible display because of its virtue of mechanical flexibility, low fabrication cost, low process temperature, and large area production. In order to achieve high performance OTFTs, increase in accumulation carrier mobility is a critical factor. Post-fabrication thermal annealing process has been known as one of the methods to achieve this by improving the crystal quality of organic semiconductor materials In this paper, we researched the properties of pentacene films with X-Ray Diffraction (XRD) and Atomic Force Microscope (AFM) analyses as different annealing temperature in N2 ambient. Electrical characterization of the pentacene based thin film transistor was also conducted by transfer length method (TLM) with different annealing temperature in Al- and Ti-pentacene junctions to confirm the Fermi level pinning phenomenon. For Al- and Ti-pentacene junctions, is was found that as the surface quality of the pentacene films changed as annealing temperature increased, the hole-barrier height (h-BH) that were controlled by Fermi level pinning were effectively reduced.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.338-338
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• 2013

Monolithic three-dimensional integrated circuits (3D-ICs) 구현 시 bonding 과정에서 발생되는 aluminum (Al) 이나 copper (Cu) 등의 interconnect metal의 확산, 열적 스트레스, 결함의 발생, 도펀트 재분포와 같은 문제들을 피하기 위해서는 저온 공정이 필수적이다. 지금까지는 polymer 기반의 bonding이나 Cu/Cu와 같은 metal 기반의 bonding 등과 같은 저온 bonding 방법이 연구되어 왔다. 그러나 이와 같은 bonding 공정들은 공정 시 void와 같은 문제가 발생하거나 공정을 위한 특수한 장비가 필수적이다. 반면, 두 물질의 합금을 이용해 녹는점을 낮추는 eutectic bonding 공정은 저온에서 공정이 가능할 뿐만 아니라 void의 발생 없이 강한 bonding 강도를 얻을 수 있다. Aluminum-germanium (Al-Ge) 및 aluminum-indium (Al-In) 등의 조합이 eutectic bonding에 이용되어 각각 $424^{\circ}C$ 및 $454^{\circ}C$의 저온 공정을 성취하였으나 여전히 $400^{\circ}C$이상의 eutectic 온도로 인해 3D-ICs의 구현 시에는 적용이 불가능하다. 이러한 metal 조합들에 비해 indium (In)과 tin (Sn)은 각각 $156^{\circ}C$ 및 $232^{\circ}C$로 굉장히 낮은 녹는점을 가지고 있기 때문에 In-Sn 조합은 약 $120^{\circ}C$ 정도의 상당히 낮은eutectic 온도를 갖는다. 따라서 본 연구팀은 In-Sn 조합을 이용하여 $200^{\circ}C$ 이하에서monolithic 3D-IC 구현 시 사용될 eutectic bonding 공정을 개발하였다. 100 nm SiO2가 증착된 Si wafer 위에 50 nm Ti 및 410 nm In을 증착하고, 다른Si wafer 위에 50 nm Ti 및 500 nm Sn을 증착하였다. Ti는 adhesion 향상 및 diffusion barrier 역할을 위해 증착되었다. In과 Sn의 두께는 binary phase diagram을 통해 In-Sn의 eutectic 온도인 $120^{\circ}C$ 지점의 조성 비율인 48 at% Sn과 52 at% In에 해당되는 410 nm (In) 그리고 500 nm (Sn)로 결정되었다. Bonding은 Tbon-100 장비를 이용하여 $140^{\circ}C$, $170^{\circ}C$ 그리고 $200^{\circ}C$에서 2,000 N의 압력으로 진행되었으며 각각의 샘플들은 scanning electron microscope (SEM)을 통해 확인된 후, 접합 강도 테스트를 진행하였다. 추가로 bonding 층의 In 및 Sn 분포를 확인하기 위하여 Si wafer 위에 Ti/In/Sn/Ti를 차례로 증착시킨 뒤 bonding 조건과 같은 온도에서 열처리하고secondary ion mass spectrometry (SIMS) profile 분석을 시행하였다. 결론적으로 본 연구를 통하여 충분히 높은 접합 강도를 갖는 In-Sn eutectic bonding 공정을 $140^{\circ}C$의 낮은 공정온도에서 성공적으로 개발하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.216-216
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• 1999

The usage of a stationary plasma thruster (SPT) ion source, invented previously for space application in Russia, in experiments with surface modifications and film deposition systems is reported here. Plasma in the SPT is formed and accelerated in electric discharge taking place in the crossed axial electric and radial magnetic fields. Brief description of the construction of specific model of SPT used in the experiments is presented. With gas flow rate 39ml/min, ion current distributions at several distances from the source are obtained. These was equal to 1~3 mA/$\textrm{cm}^2$ within an ion beam ejection angle of $\pm$20$^{\circ}$with discharge voltage 160V for Ar as a working gas. Such an extremely high ion current density allows us to obtain the Ti metal films with deposition rate of $\AA$/sec by sputtering of Ti target. It is shown a possibility of using of reactive gases in SPT (O2 and N2) along with high purity inert gases used for cathode to prevent the latter contamination. It is shown the SPT can be operated at the discharge and accelerating boltages up to 600V. The results of presented experiments show high promises of the SPT in sputtering and surface modification systems for deposition of oxide thin films on Si or polymer substrates for semiconductor devices, optical coatings and metal corrosion barrier layers. Also, we have been tried to establish in application of the modeling expertise gained in electric and ionic propulsion to permit numerical simulation of additional processing systems. In this mechanism, it will be compared with conventional DC sputtering for film microstructure, chemical composition and crystallographic considerations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.22-29
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• 2006

We demonstrate highly manufacturable Multi-channel Field Effect Transistor (McFET) on bulk Si wafer. McFET shows excellent transistor characteristics, such as $5{\sim}6 times higher drive current than planar MOSFET, ideal subthreshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency, maintaining the same source/drain resistance as that of a planar transistor due to the unique feature of McFET. And suitable threshold voltage ($V_T$) for SRAM operation and high static noise margin (SNM) are achieved by using TiN metal gate electrode.