• Title/Summary/Keyword: Threshold charge density

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A Device Parameter Extraction Method for Thin Film SOI MOSFETs (얇은 박막 SOI (Silicon-On-Insulator) MOSFET 에서의 소자 변수 추출 방법)

  • Park, Sung-Kye;Kim, Choong-Ki
    • Proceedings of the KIEE Conference
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    • 1992.07b
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    • pp.820-824
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    • 1992
  • An accurate method for extracting both Si film doping concentration and front or back silicon-to-oxide fixed charge density of fully depleted SOI devices is proposed. The method utilizes the current-to-voltage and capacitance-to-voltage characteristics of both SOI NMOSFET and PMOSFET which have the same doping concentration. The Si film doping concentration and the front or back silicon-to-oxide fixed charge density are extracted by mainpulating the respective threshold voltages of the SOI NMOSFET and PMOSFET according to the back surface condition (accumulation or inversion) and the capacitance-to-voltage characteristics of the SOI PMOSFET. Device simulations show that the proposed method has less than 10% errors for wide variations of the film doping concentration and the front or the back silicon-to-oxide fixed charge density.

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Hot-Carrier-Induced Degradation in Submicron MOS Transistors (Submicron MOS 트랜지스터의 뜨거운 운반자에 의한 노쇠현상)

  • 최병진;강광남
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.7
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    • pp.780-790
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    • 1988
  • We have studied the hot-carrier-induced degradation caused by the high channel electric field due to the decrease of the gate length of MOSFET used in VLSI. Under DC stress, the condition in which maximum substrate current occures gave the worst degradation. Under AC dynamic stress, other conditions, the pulse shape and the falling rate, gave enormous effects on the degradation phenomena, especially at 77K. Threshold voltage, transconductance, channel conductance and gate current were measured and compared under various stress conditions. The threshold voltage was almost completely recovered by hot-injection stress as a reverse-stress. But, the transconductance was rapidly degraded under hot-hole injection and recovered by sequential hot-electron stress. The Si-SiO2 interface state density was analyzed by a charge pumping technique and the charge pumping current showed the same trend as the threshold voltage shift in degradation process.

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A Compact Quantum Model for Cylindrical Surrounding Gate MOSFETs using High-k Dielectrics

  • Vimala, P.;Balamurugan, N.B.
    • Journal of Electrical Engineering and Technology
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    • v.9 no.2
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    • pp.649-654
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    • 2014
  • In this paper, an analytical model for Surrounding Gate (SG) metal-oxide- semiconductor field effect transistors (MOSFETs) considering quantum effects is presented. To achieve this goal, we have used variational approach for solving the Poission and Schrodinger equations. This model is developed to provide an analytical expression for inversion charge distribution function for all regions of device operation. This expression is used to calculate the other important parameters like inversion charge density, threshold voltage, drain current and gate capacitance. The calculated expressions for the above parameters are simple and accurate. This paper also focuses on the gate tunneling issue associated with high dielectric constant. The validity of this model was checked for the devices with different dimensions and bias voltages. The calculated results are compared with the simulation results and they show good agreement.

Interface Trap Effects on the Output Characteristics of GaN Schottky Barrier MOSFET (GaN Schottky Barrier MOSFET의 출력 전류에 대한 계면 트랩의 영향)

  • Park, Byeong-Jun;Kim, Han-Sol;Hahm, Sung-Ho
    • Journal of Sensor Science and Technology
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    • v.31 no.4
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    • pp.271-277
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    • 2022
  • We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the Nit distribution using TCAD simulation. As interface trap number density (Nit) increased, the threshold voltage increased while the drain current density decreased. Under Nit=5.0×1010 cm-2 condition, the threshold voltage was 3.2 V for VDS=1 V, and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the Nit distribution type, there was an increase in the subthreshold swing (SS) following an increase in Nit. Under U-shaped Nit distribution, it was confirmed that the SS varied depending on the gate voltage. The interface fixed charge (Qf) caused an shift in the threshold voltage and increased the off-state current collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectronic circuit provided the surface state is significantly reduced.

Electrical Stimulation Parameters in Normal and Degenerate Rabbit Retina (정상 망막과 변성 망막을 위한 전기자극 파라미터)

  • Jin, Gye-Hwan;Goo, Yong-Sook
    • Progress in Medical Physics
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    • v.19 no.1
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    • pp.73-79
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    • 2008
  • Retinal prosthesis is regarded as the most feasible method for the blind caused by retinal diseases such as retinitis pigmentosa (RP) or age related macular degeneration (AMD). Recently Korean consortium launched for developing retinal prosthesis. One of the prerequisites for the success of retinal prosthesis is the optimization of the electrical stimuli applied through the prosthesis. Since electrical characteristics of degenerate retina are expected to differ from those of normal retina, we performed voltage stimulation experiment both in normal and degenerate retina to provide a guideline for the optimization of electrical stimulation for the upcoming prosthesis. After isolation of retina, retinal patch was attached with the ganglion cell side facing the surface of microelectrode arrays (MEA). $8{\times}8$ grid layout MEA (electrode diameter: $30{\mu}m$, electrode spacing: $200{\mu}m$, and impedance: $50k{\Omega}$ at 1 kHz) was used to record in-vitro retinal ganglion cell activity. Mono-polar electrical stimulation was applied through one of the 60 MEA channel, and the remaining channels were used for recording. The electrical stimulus was a constant voltage, charge-balanced biphasic, anodic-first square wave pulse without interphase delay, and 50 trains of pulse was applied with a period of 2 sec. Different electrical stimuli were applied. First, pulse amplitude was varied (voltage: $0.5{\sim}3.0V$). Second, pulse duration was varied $(100{\sim}1,200{\mu}s)$. Evoked responses were analyzed by PSTH from averaged data with 50 trials. Charge density was calculated with Ohm's and Coulomb's law. In normal retina, by varying the pulse amplitude from 0.5 to 3V with fixed duration of $500{\mu}s$, the threshold level for reliable ganglion cell response was found at 1.5V. The calculated threshold of charge density was $2.123mC/cm^2$. By varying the pulse duration from 100 to $1,200{\mu}s$ with fixed amplitude of 2V, the threshold level was found at $300{\mu}s$. The calculated threhold of charge density was $1.698mC/cm^2$. Even after the block of ON-pathway with L-(1)-2-amino-4-phosphonobutyric acid (APB), electrical stimulus evoked ganglion cell activities. In this APB-induced degenerate retina, by varying the pulse duration from 100 to $1200{\mu}s$ with fixed voltage of 2 V, the threshold level was found at $300{\mu}s$, which is the same with normal retina. More experiment with APB-induced degenerate retina is needed to make a clear comparison of threshold of charge density between normal and degenerate retina.

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Interface trap density distribution in 3D sequential Integrated-Circuit and Its effect (3차원 순차적 집적회로에서 계면 포획 전하 밀도 분포와 그 영향)

  • Ahn, TaeJun;Lee, Si Hyun;Yu, YunSeop
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.12
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    • pp.2899-2904
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    • 2015
  • This paper introduces about the effect on $I_{DS}-V_{GS}$ characteristic of transistor that interface trap charge is created by damage due to heat in a 3D sequential inverter. A interface trap charge distribution in oxide layer in a 3D sequential inverter is extracted using two-dimensional device simulator. The variation of threshold voltage of top transistor according to the gate voltage variation of bottom transistor is also described in terms of Inter Layer Dielectric (ILD) length of 3D sequential inverter, considering the extracted interface trap charge distribution. The extracted interface trap density distribution shows that the bottom $HfO_2$ layer and both the bottom and top $SiO_2$ layer were relatively more affected by heat than the top $HfO_2$ layer with latest process. The threshold voltage variations of the shorter length of ILD in 3D sequential inverter under 50nm is higher than those over 50nm. The $V_{th}$ variation considering the interface trap charge distribution changes less than that excluding it.

The Pulsed Id-Vg methodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

  • Young, Chadwin D.;Heh, Dawei;Choi, Ri-No;Lee, Byoung-Hun;Bersuker, Gennadi
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.2
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    • pp.79-99
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    • 2010
  • Pulsed current-voltage (I-V) methods are introduced to evaluate the impact of fast transient charge trapping on the performance of high-k dielectric transistors. Several pulsed I-V measurement configurations and measurement requirements are critically reviewed. Properly configured pulsed I-V measurements are shown to be capable of extracting such device characteristics as trap-free mobility, trap-induced threshold voltage shift (${\Delta}V_t$), as well as effective fast transient trap density. The results demonstrate that the pulsed I-V measurements are an essential technique for evaluating high-$\kappa$ gate dielectric devices.

Characteristics of Damage on Photosensor Irradiated by Intense Illumination : Thermal Diffusion Model (고섬광에 노출된 광센서의 손상 특성 : 열확산 모델)

  • Kwon, Chan-Ho;Shin, Myeong-Suk;Hwang, Hyon-Seok;Kim, Hong-Lae;Kim, Seong-Shik;Park, Min-Kyu
    • Journal of the Korea Institute of Military Science and Technology
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    • v.15 no.2
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    • pp.201-207
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    • 2012
  • Pulsed lasers at the 613 nm and 1064 nm wavelengths on nanoseconds have been utilized to characterize the damage on Si photodiode exposed to intense illumination. Morphological damages and structural changes at sites on the photodiode irradiated during microseconds of laser pulses were analyzed by FE-SEM images and XRD patterns, respectively. The removal of oxide coating, ripple, melting marks, ridges, and crater on photodiodes were definitely observed in order of increasing the pulse intensities generated above the damage threshold. Then, the degradation in photosensitivity of the Si photodiode irradiated by high power density pulses was measured as a function of laser irradiation time at the various wavelengths. The free charge carrier and thermal diffusion mechanisms could have been invoked to characterize the damage. The relative photosensitivity data calculated using the thermal diffusion model proposed in this paper have been compared with the experimental data irradiated above the damage threshold.

Effect of Asymmetric Electrode Structure on Electron Emission of the Pb(Zr0.8Ti0.2)O3 Ferroelectric Cathode (Pb(Zr0.8Ti0.2)O3강유전 음극에서 비대칭 전극구조가 전자 방출 특성에 미치는 영향)

  • 박지훈;김용태;윤기현;김태희;박경봉
    • Journal of the Korean Ceramic Society
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    • v.39 no.1
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    • pp.92-98
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    • 2002
  • To investigate the electrode structural effect on the ferroelectric electron emission, the electric field distribution in a 2-dimensional structure was calculated as a function of upper electrode diameter, and the switching charge density and emission charge were measured simultaneously. The simulation of the electric field distribution showed that an asymmetric electrode structure could cause a stray field on the bare surface of the ferroelectric cathode near the edge of upper electrode. The distance of stray field from the electrode edge increased with increasing ferroelectric thickness, but it did not depend on the upper electrode diameter. The switching charge density increased more on the cathode with smaller upper electrode diameter. This was attributed to the stray field on the bare ferroelectric surface near the electrode edge, because the stray field for the asymmetric ferroelectric cathode enhanced polarization switching near the electrode edge. From the switching charge density, the distance of stray field from the electrode edge was calculated as about 11-14${\mu}{\textrm}{m}$. The threshold voltage of electron emission was 61-68 kV/cm, which was almost 3 times lager than the coercive voltage. The threshold voltage was not determined just by coercive voltage, but by strength and distance of the stray-field, which largely depended on the geometrical structure of ferroelectric cathode.

Characterization of the Vertical Position of the Trapped Charge in Charge-trap Flash Memory

  • Kim, Seunghyun;Kwon, Dae Woong;Lee, Sang-Ho;Park, Sang-Ku;Kim, Youngmin;Kim, Hyungmin;Kim, Young Goan;Cho, Seongjae;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.2
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    • pp.167-173
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    • 2017
  • In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.