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http://dx.doi.org/10.6109/jkiice.2015.19.12.2899

Interface trap density distribution in 3D sequential Integrated-Circuit and Its effect  

Ahn, TaeJun (Department of Electronic Engineering, Hankyong National University)
Lee, Si Hyun (Department of Information and Communication, Dong-Seoul University)
Yu, YunSeop (Department of Electrical, Electronic and Control Engineering, Hankyong National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.19, no.12, 2015 , pp. 2899-2904 More about this Journal
Abstract
This paper introduces about the effect on $I_{DS}-V_{GS}$ characteristic of transistor that interface trap charge is created by damage due to heat in a 3D sequential inverter. A interface trap charge distribution in oxide layer in a 3D sequential inverter is extracted using two-dimensional device simulator. The variation of threshold voltage of top transistor according to the gate voltage variation of bottom transistor is also described in terms of Inter Layer Dielectric (ILD) length of 3D sequential inverter, considering the extracted interface trap charge distribution. The extracted interface trap density distribution shows that the bottom $HfO_2$ layer and both the bottom and top $SiO_2$ layer were relatively more affected by heat than the top $HfO_2$ layer with latest process. The threshold voltage variations of the shorter length of ILD in 3D sequential inverter under 50nm is higher than those over 50nm. The $V_{th}$ variation considering the interface trap charge distribution changes less than that excluding it.
Keywords
3D sequential integration; Interface trap charge density distribution; 3D sequential inverter; threshold voltage;
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