• Journal of the Microelectronics and Packaging Society
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• v.29 no.3
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• pp.43-48
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• 2022

In this study, simulation method was developed to improve the accuracy of the warpage simulation based on the equivalent anisotropic viscoelastic model. First, a package with copper traces and bumps was modeled to implement anisotropic viscoelastic behavior. Then, equivalent anisotropic viscoelastic properties and thermal expansion coefficient for the bump region were derived through the representative volume element model. A thermal cycle of 0 to 125 degrees was applied to the package based on the derived mechanical properties, and the warpage according to the thermal cycle was simulated. To verify the simulation results, the actual package was manufactured, and the warpage with respect to the thermal cycle was measured through shadow moiré interferometer. As a result, by applying the equivalent anisotropic viscoelastic model, it was possible to calculate the warpage of the package within 5 ㎛ error and predict the shape of the warpage.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.33-38
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• 2013

In this study, both a finite element analysis and an experimental analysis are executed to investigate the mechanical characteristics of dielectric material effects on warpage. Also, viscoelastic material properties are measured by DMA and are considered in warpage simulation. A finite element analysis is done by using both thermal elastic analysis and a thermo-viscoelastic analysis to predict the nonlinear effects. For experimental study, specimens warpage of non-symmetric structure with body size of $22.5{\times}22.5$ mm, $37.5{\times}37.5$ mm and $42.5{\times}42.5$ mm are measured under the reflow temperature condition. From the analysis results, experimental warpage is not similar to FEA results using thermal elastic analysis but similar to FEA results using thermo-viscoelastic analysis. Also, its effect on substrate warpage is increased as core thickness is decreased and body size is getting larger. These FEA and the experimental results show that the nonlinear characteristics of dielectric material play an important role on substrate warpage. Therefore, it is strongly recommended that non-linear behavior characteristics of a dielectric material should be considered to control warpage of FCBGA substrate under conditions of geometry, structure and manufacturing process and so on.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.89-93
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• 2020

Complex warpage behavior of the electronic packages causes internal stress so many kinds of mechanical failure occur such as delamination or crack. Efforts to predict the warpage behavior accurately in order to prevent the decrease in yield have been approached from various aspects. For warpage prediction, silicon is generally treated as a homogeneous material, therefore it is described as showing no warpage behavior due to thermal loading. However, it was reported that warpage is actually caused by residual stress accumulated during grinding and polishing in order to make silicon wafer thinner, which make silicon wafer inhomogeneous through thickness direction. In this paper, warpage behavior of the single-side polished wafer at solder reflow temperature, the highest temperature in packaging processes, was measured using 3D digital image correlation (DIC) method. Mechanism was verified by measuring coefficient of thermal expansion (CTE) of both mirror-polished surface and rough surface.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.67-73
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• 2020

In this paper, we used FEM technique to perform warpage and von Mises stress analysis on PCB according to the cavity structures of embedded PCB for FCCSP and the types of prepreg material. One-half substrate model and static analysis are applied to the FEM. According to the analysis results of the warpage, as the gap between the cavity and the chip increased, warpage increased and warpage increased when prepreg material with higher modularity and thermal expansion coefficient was applied. The analysis results of the von Mises stress show that the effect of the gap between the cavity and the chip varies depending on prepreg material. In other words, when material whose coefficient of thermal expansion is significantly higher than that of core material, the stress increased as the gap between the cavity and the chip increased. When the prepreg with the coefficient of thermal expansion lower than the core material is applied, the result of stress is opposite. These results indicate that from a reliability perspective, there is a correlation between the structure of the cavity where embedded chips are loaded and prepreg material.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 1999.03b
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• pp.136-142
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• 1999

The injection molded part shrinks in the process of solidification by the amount of the coefficient of linear thermal expansion multiplied by the temperature difference between the coefficient of linear thermal expansion multiplied by the temperature difference between the room temperature and the temperature at which the solid structure is formed in the mold And it is called warpage for this type of deformation that shrinkage are not uniform throughout the injection molded part. To predict warpage phenomena in the articles the results obtained theoretically from the change of mold temperature fiber content of composites have been compared with exsperimental results.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.41-45
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• 2018

As the size of semiconductor chip shrinks, the electronic industry has been paying close attention to fan-out wafer level packaging (FO-WLP) as an emerging solution to accommodate high input and output density. FO-WLP also has several advantages, such as thin thickness and good thermal resistance, compared to conventional packaging technologies. However, one major challenge in current FO-WLP manufacturing process is to control wafer warpage, caused by the difference of coefficient of thermal expansion and Young's modulus among the materials. Wafer warpage induces misalignment of chips and interconnects, which eventually reduces product quality and reliability in high volume manufacturing. In order to control wafer warpage, it is necessary to understand the effect of material properties and design parameters, such as chip size, chip to mold ratio, and carrier thickness, during packaging processes. This paper focuses on the effects of thickness of chip and molding compound on 12" wafer warpage after PMC of EMC using finite element analysis. As a result, the largest warpage was observed at specific thickness ratio of chip and EMC.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.2 s.39
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• pp.1-7
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• 2006

In this paper, warpage magnitude and shape of printed-circuit board in case that properties of core and thickness of solder resist are varied are investigated. The cause of warpage is coefficient of thermal expansion differences of stacked materials. Therefore, we need small difference of coefficient of thermal expansion that laminated material, and need to decrease asymmetric of top side and bottom side in structure shape. Also, we can control occurrence of warpage heightening hardness of core in laminated material. Composite material that make core are exploited in connection with the structural bending twisting coupling resulting from directional properties of fiber reinforced composite materials and from ply stacking sequence. If we use such characteristic, we can control warpage with change of material properties. In this paper, warpage of two layer stacked chip scale package is investigated, and evaluate improvement result using an experiment and finite element method tool.

• Composites Research
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• v.25 no.4
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• pp.117-125
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• 2012

Warpage of the film insert molded (FIM) part is caused by an asymmetric residual stress distribution. Asymmetric residual stress and temperature distribution is generated by the retarded heat transfer in the perpendicular direction to the attached film surface. Since warpage was not prevented by controlling injection molding conditions, glass fiber (GF) filled composites were employed as substrates for film insert molding to minimize the warpage. Distribution of short GFs was evaluated by using micro-CT equipment. Proper models for micro mechanics, anisotropic thermal expansion coefficients, and closure approximation should be selected in order to calculate fiber orientation tensor and warpage of the FIM part with the composite substrate. After six kinds of micro mechanics models, three models of the thermal expansion coefficient and five models of the closure approximation had been considered, the Mori-Tanaka model, the Rosen and Hashin model, and the third orthotropic closure approximation were selected in this study. The numerically predicted results on fiber orientation tensor and warpage were in good agreement with experimental results and effects of GF reinforcement on warpage of the FIM composite specimen were identified by the numerical results.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.61-67
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• 2020

In this paper, we calculated the warpage of bare substrates and chip attached substrates by using FEM (Finite Element Method), and compared and analyzed the effect of the chips' attachment on warpage. Also, the effects of layer thickness of substrates for reducing warpage were analyzed and the conditions of layer thickness were analyzed by signal-to-noise ratio of Taguchi method. According to the analysis results, the direction of warpage pattern in substrates can change when chips are attached. Also, the warpage decreases as the difference in the CTE (coefficient of thermal expansion) between the top and bottom of the package decreases and the stiffness of the package increases after chips are loaded. In addition, according to the impact analysis of design parameters on substrates where chips are not attached, in order to reduce warpage, the inner layers of the circuit layer Cu1 and Cu4 has be controlled first, and then concentrated on the thickness of the solder resist on the bottom side and the thickness of the prepreg layer between Cu1 and Cu2.

• Journal of the Semiconductor & Display Technology
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• v.15 no.4
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• pp.1-9
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• 2016

The warpage on mobile phone camera packages occurs due to the CTE(Coefficient of Thermal Expansion) mismatch between a thin silicon die and a substrate. The warpage in the optical instruments such as camera module has an effect on the field curvature, which is one of the factors degrading the optical performance and the product yield. In this paper, we studied the effect of die bonding epoxy on the package and optical performance of mobile phone camera packages. We calculated the warpages of camera module packages by using a finite element analysis, and their shapes were in good agreement showing parabolic curvature. We also measured the warpages and through-focus MTF of camera module specimens with experiments. The warpage was improved on an epoxy with low elastic modulus at both finite element analysis and experiment results, and the MTF performance increased accordingly. The results show that die bonding epoxy affects the warpage generated on the image sensor during the packaging process, and this warpage eventually affects the optical performance associated with the field curvature.