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http://dx.doi.org/10.6117/kmeps.2020.27.3.061

Study on Design Parameters of Substrate for PoP to Reduce Warpage Using Finite Element Method  

Cho, Seunghyun (Department of Mechanical Engineering, Dongyang Mirae University)
Lee, Sangsoo (Department of Mechanical Engineering, Dongyang Mirae University)
Publication Information
Journal of the Microelectronics and Packaging Society / v.27, no.3, 2020 , pp. 61-67 More about this Journal
Abstract
In this paper, we calculated the warpage of bare substrates and chip attached substrates by using FEM (Finite Element Method), and compared and analyzed the effect of the chips' attachment on warpage. Also, the effects of layer thickness of substrates for reducing warpage were analyzed and the conditions of layer thickness were analyzed by signal-to-noise ratio of Taguchi method. According to the analysis results, the direction of warpage pattern in substrates can change when chips are attached. Also, the warpage decreases as the difference in the CTE (coefficient of thermal expansion) between the top and bottom of the package decreases and the stiffness of the package increases after chips are loaded. In addition, according to the impact analysis of design parameters on substrates where chips are not attached, in order to reduce warpage, the inner layers of the circuit layer Cu1 and Cu4 has be controlled first, and then concentrated on the thickness of the solder resist on the bottom side and the thickness of the prepreg layer between Cu1 and Cu2.
Keywords
PoP; PCB; Taguchi; Warpage; FEM;
Citations & Related Records
Times Cited By KSCI : 5  (Citation Analysis)
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