1 |
L. Boettcher, S. Karaszkiwicz, D. Manessis, and A. Ostmann, "Embedded chip technology: Technologies, applications, and future developments", Proc. SMTA, San Diego, 9 (2012).
|
2 |
C. T. Ko, S. Chen, C. W. Chiang, T. Y. Kuo, Y. C. Shih, and Y. H. Chen, "Embedded active device packaging technology for next-generation chip-in-substrate package, CiSP", Proc. 56th Electronics Components and Technology Conference (ECTC), San Diego, 322, IEEE (2006).
|
3 |
L. Boettcher, D. Manessis, A. Ostmann, and H. Reichel, "Realization of system in package modules by embedding of chips", Proc. IMAPS Device Packaging, Scottsdale, 397 (2008).
|
4 |
H. W. Park, S. H. Cho, J. Kress, A. Bruderer, and N. Galster, "Dielectric composite material with good performance and process ability for embedding of active and passive components into PCBs", Proc. 63rd Electronic Components and Technology Conference (ECTC), Las Vegas, 1325, IEEE (2013).
|
5 |
S. H. Cho, D. H. Kim, Y. G. Oh, J. T. Lee, and S. S. Cha, "A Study on the Parameters of Design for Warpage reduction of Passive components Embedded Substrate for PoP", J. Microelectron. Packag. Soc., 22(1), 75 (2015).
DOI
|
6 |
D. H. Park and T. S. Oh, "Reliability Characteristics of a Package-on-Package with Temperature/Humidity Test, Temperature Cycling Test, and High Temperature Storage Test", J. Microelectron. Packag. Soc., 23(3), 43 (2016).
DOI
|
7 |
S. Yi, K. O. Kim, D. W. Lee, H. W. Kim, and T. S. Jung, "Embedded passive device technology for wireless mobile devices", Microelectronics International, 30(1), 33 (2013).
DOI
|
8 |
T. Snyder and S. Yi, "Thermal performance of embedded active chips", Proc. 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 209 (2014).
|
9 |
M. Y. Tsi, C. H. J. Hsu, and C. T. O. Wang, "Investigation of thermomechanical behaviors of flip chip BGA packages during manufacturing process and thermal cycling", Components and Packaging Technologies, 27(3), 568 (2004).
DOI
|
10 |
R. Darveaux, C. Reichman, and N. Islam, "Interface Failure in Lead Free Solder Joints", Proc. 56th Electronic Components and Technology Conference (ECTC), San diego, 906 (2006).
|
11 |
S. H. Cho, S. J. Cho, and J. Y. Lee, "Estimation of warpage and thermal stress of IVHs in flip-hip ball grid arrays package by FEM", Microelectronics Reliability, 48(2), 300 (2008).
DOI
|
12 |
J. H. Lau and S. W. R. Lee, "Effects of Build-Up Printed Circuit Board Thickness in the Solder Joint Reliability of a Wafer Level Chip Scale Package(WLCSP)", Trans. Comp. Packag. Technol., 25(1), 51 (2002).
|
13 |
S. H. Cho, H. I. Jung, and O. C. Bae, "Numerical Analysis on the Design Variables and Thickness Deviation Effects on Warpage of Substrate for FCCSP", J. Microelectron. Packag. Soc., 19(3), 57 (2012).
DOI
|
14 |
W. Sun, W. H. Zhu, C. K. Wang, A. Y. S. Sun, and H. B. Tan, "Warpage Simulation and DOE Analysis with Application in Package-on-Package Development", Proc. 9th Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, Euro-SimE, Freiburg, 244, IEEE (2008).
|
15 |
Y. L. Tzeng, N. Kao, E. Chen, J. Y. Lai, Y. P. Wang, and C. S. Hsiao, "Warpage and Stress Characteristic Analyses on Package-on-Package (PoP) Structure", Proc. 9th Electronics Packaging Technology Conference (EPTC), Singapore, 482, IEEE (2007).
|
16 |
W. Sun, W. H. Zhu, K. S. Le, and H. B. Tan, "Simulation Study on the Warpage Behavior and Board-level Temperature Cycling Reliability of PoP Potentially for High-speed Memory Packaging", Proc. International Conference on Electronic Packaging Technology & High Density Packaging (ICEPTHDP), Shanghai, 978, IEEE (2008).
|
17 |
C. M. Ryder, "Embedded components: A comparative analysis of reliability", Proc. IPC APEX, Las Vegas, 3156 (2011).
|
18 |
S. H. Cho D. H. Kim, Y. G. Oh, J. T. Lee, and S. S. Cha, "A Study on the Parameters of Design for Warpage reduction of Passive components Embedded Substrate for PoP", J. Microelectron. Packag. Soc., 22(1), 75 (2015).
DOI
|