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http://dx.doi.org/10.6117/kmeps.2018.25.1.041

Warpage Analysis during Fan-Out Wafer Level Packaging Process using Finite Element Analysis  

Kim, Geumtaek (School of Mechanical, Aerospace and Nuclear Engineering, UNIST)
Kwon, Daeil (School of Mechanical, Aerospace and Nuclear Engineering, UNIST)
Publication Information
Journal of the Microelectronics and Packaging Society / v.25, no.1, 2018 , pp. 41-45 More about this Journal
Abstract
As the size of semiconductor chip shrinks, the electronic industry has been paying close attention to fan-out wafer level packaging (FO-WLP) as an emerging solution to accommodate high input and output density. FO-WLP also has several advantages, such as thin thickness and good thermal resistance, compared to conventional packaging technologies. However, one major challenge in current FO-WLP manufacturing process is to control wafer warpage, caused by the difference of coefficient of thermal expansion and Young's modulus among the materials. Wafer warpage induces misalignment of chips and interconnects, which eventually reduces product quality and reliability in high volume manufacturing. In order to control wafer warpage, it is necessary to understand the effect of material properties and design parameters, such as chip size, chip to mold ratio, and carrier thickness, during packaging processes. This paper focuses on the effects of thickness of chip and molding compound on 12" wafer warpage after PMC of EMC using finite element analysis. As a result, the largest warpage was observed at specific thickness ratio of chip and EMC.
Keywords
Fan out wafer level package; Warpage; EMC; FEA;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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